NewCSR: set legal init value to WARL Field

src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala

@@ -13,27 +13,35 @@ import chisel3.experimental.noPrefix
 
 object CSRBundles {
   class XtvecBundle extends CSRBundle {
-    val mode = XtvecMode(1, 0, wNoFilter)
-    val addr = WARL(63, 2, wNoFilter)
+    val mode = XtvecMode(1, 0, wNoFilter).withReset(0.U)
+    val addr = WARL(63, 2, wNoFilter).withReset(0.U)
   }
 
   class CauseBundle extends CSRBundle {
-    val Interrupt = RW(63)
-    val ExceptionCode = RW(62, 0)
+    val Interrupt = RW(63).withReset(0.U)
+    val ExceptionCode = RW(62, 0).withReset(0.U)
   }
 
   class Counteren extends CSRBundle {
     // Todo: remove reset after adding mcounteren in difftest
     val CY = RW(0).withReset(0.U)
-    val TM = RW(1)
-    val IR = RW(2)
-    val HPM = RW(31, 3)
+    val TM = RW(1).withReset(0.U)
+    val IR = RW(2).withReset(0.U)
+    val HPM = RW(31, 3).withReset(0.U)
   }
 
   class OneFieldBundle extends CSRBundle {
     val ALL = RW(63, 0)
   }
 
+  class FieldInitBundle extends OneFieldBundle {
+    this.ALL.setRW().withReset(0.U)
+  }
+
+  class XtvalBundle extends FieldInitBundle
+
+  class XtinstBundle extends FieldInitBundle
+
   abstract class EnvCfg extends CSRBundle {
     // Set all fields as RO in base class
     val STCE  = RO(    63).withReset(0.U) // Sstc Enable

src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala

@@ -15,6 +15,7 @@ import xiangshan.backend.fu.NewCSR.CSRDefines.{
 }
 import xiangshan.backend.fu.NewCSR.CSRFunc._
 import xiangshan.backend.fu.NewCSR.CSREvents._
+import xiangshan.backend.fu.NewCSR.CSRBundles._
 import CSRConfig._
 import utility.SignExt
 import scala.collection.immutable.SeqMap
@@ -107,7 +108,7 @@ trait DebugLevel { self: NewCSR =>
 // tselect
 class TselectBundle(triggerNum: Int) extends CSRBundle{
   override val len: Int = log2Up(triggerNum)
-  val ALL = WARL(len - 1, 0, wNoEffectWhen(WriteTselect))
+  val ALL = WARL(len - 1, 0, wNoEffectWhen(WriteTselect)).withReset(0.U)
   def WriteTselect(wdata: UInt) = {
     wdata >= triggerNum.U
   }
@@ -117,7 +118,7 @@ class TselectBundle(triggerNum: Int) extends CSRBundle{
 class Tdata1Bundle extends CSRBundle{
   val TYPE    = Tdata1Type(63, 60, wNoFilter).withReset(Tdata1Type.Disabled)
   val DMODE   = RW(59).withReset(0.U)
-  val DATA    = RW(58, 0)
+  val DATA    = RW(58, 0).withReset(0.U)
 
   def getTriggerAction: CSREnumType = {
     val res = Wire(new Mcontrol)
@@ -248,9 +249,7 @@ object TrigMatch extends CSREnum with WARLApply {
 
 
 // tdata2
-class Tdata2Bundle extends CSRBundle{
-  val ALL = RW(63, 0)
-}
+class Tdata2Bundle extends OneFieldBundle
 
 // Tinfo
 class TinfoBundle extends CSRBundle{
@@ -268,9 +267,7 @@ class TcontrolBundle extends CSRBundle{
 }
 
 // Dscratch
-class DscratchBundle extends CSRBundle{
-  val ALL   = RW(63, 0)
-}
+class DscratchBundle extends OneFieldBundle
 
 
 class DcsrBundle extends CSRBundle {

src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala

@@ -46,9 +46,7 @@ trait HypervisorLevel { self: NewCSR =>
   })
     .setAddr(CSRs.hie)
 
-  val htimedelta = Module(new CSRModule("Htimedelta", new CSRBundle {
-    val VALUE = RW(63, 0)
-  }))
+  val htimedelta = Module(new CSRModule("Htimedelta"))
     .setAddr(CSRs.htimedelta)
 
   val hcounteren = Module(new CSRModule("Hcounteren", new Counteren))
@@ -70,9 +68,7 @@ trait HypervisorLevel { self: NewCSR =>
   })
     .setAddr(CSRs.henvcfg)
 
-  val htval = Module(new CSRModule("Htval", new CSRBundle {
-    val ALL = RW(63, 0)
-  }) with TrapEntryHSEventSinkBundle)
+  val htval = Module(new CSRModule("Htval", new XtvalBundle) with TrapEntryHSEventSinkBundle)
     .setAddr(CSRs.htval)
 
   val hip = Module(new CSRModule("Hip", new HipBundle)
@@ -126,9 +122,7 @@ trait HypervisorLevel { self: NewCSR =>
   val hviprio2 = Module(new CSRModule("Hviprio2", new Hviprio2Bundle))
     .setAddr(CSRs.hviprio2)
 
-  val htinst = Module(new CSRModule("Htinst", new CSRBundle {
-    val ALL = RW(63, 0)
-  }) with TrapEntryHSEventSinkBundle)
+  val htinst = Module(new CSRModule("Htinst", new XtinstBundle) with TrapEntryHSEventSinkBundle)
     .setAddr(CSRs.htinst)
 
   val hgatp = Module(new CSRModule("Hgatp", new HgatpBundle) {
@@ -203,10 +197,10 @@ class HstatusBundle extends CSRBundle {
   val SPV   = VirtMode(7)
   val SPVP  = RW(8)
   val HU    = RW(9)
-  val VGEIN = HstatusVgeinField(17, 12, wNoFilter, rNoFilter)
-  val VTVM  = RW(20)
-  val VTW   = RW(21)
-  val VTSR  = RW(22)
+  val VGEIN = HstatusVgeinField(17, 12, wNoFilter, rNoFilter).withReset(0.U)
+  val VTVM  = RW(20).withReset(0.U)
+  val VTW   = RW(21).withReset(0.U)
+  val VTSR  = RW(22).withReset(0.U)
   val VSXL  = XLENField(33, 32).withReset(XLENField.XLEN64)
 
 }
@@ -246,7 +240,7 @@ class HvienBundle extends InterruptEnableBundle {
 }
 
 class HgeieBundle extends CSRBundle {
-  val ie = RW(GEILEN, 1)
+  val ie = RW(GEILEN, 1).withReset(0.U)
   // bit 0 is read only 0
 }
 
@@ -333,8 +327,8 @@ class HgatpBundle extends CSRBundle {
   val MODE = HgatpMode(63, 60, wNoFilter).withReset(HgatpMode.Bare)
   // WARL in privileged spec.
   // RW, since we support max width of VMID
-  val VMID = RW(44 - 1 + VMIDLEN, 44)
-  val PPN = RW(43, 0)
+  val VMID = RW(44 - 1 + VMIDLEN, 44).withReset(0.U)
+  val PPN = RW(43, 0).withReset(0.U)
 }
 
 class HEnvCfg extends EnvCfg {

src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala

@@ -164,7 +164,7 @@ trait MachineLevel { self: NewCSR =>
     .setAddr(CSRs.mcountinhibit)
 
   val mhpmevents: Seq[CSRModule[_]] = (3 to 0x1F).map(num =>
-    Module(new CSRModule(s"Mhpmevent$num") with HasPerfEventBundle {
+    Module(new CSRModule(s"Mhpmevent$num", new MhpmeventBundle) with HasPerfEventBundle {
       regOut := perfEvents(num - 3)
     })
       .setAddr(CSRs.mhpmevent3 - 3 + num)
@@ -178,10 +178,10 @@ trait MachineLevel { self: NewCSR =>
   })
     .setAddr(CSRs.mepc)
 
-  val mcause = Module(new CSRModule("Mcause", new McauseBundle) with TrapEntryMEventSinkBundle)
+  val mcause = Module(new CSRModule("Mcause", new CauseBundle) with TrapEntryMEventSinkBundle)
     .setAddr(CSRs.mcause)
 
-  val mtval = Module(new CSRModule("Mtval") with TrapEntryMEventSinkBundle)
+  val mtval = Module(new CSRModule("Mtval", new XtvalBundle) with TrapEntryMEventSinkBundle)
     .setAddr(CSRs.mtval)
 
   val mip = Module(new CSRModule("Mip", new MipBundle)
@@ -272,10 +272,10 @@ trait MachineLevel { self: NewCSR =>
     }
   }).setAddr(CSRs.mip)
 
-  val mtinst = Module(new CSRModule("Mtinst") with TrapEntryMEventSinkBundle)
+  val mtinst = Module(new CSRModule("Mtinst", new XtinstBundle) with TrapEntryMEventSinkBundle)
     .setAddr(CSRs.mtinst)
 
-  val mtval2 = Module(new CSRModule("Mtval2") with TrapEntryMEventSinkBundle)
+  val mtval2 = Module(new CSRModule("Mtval2", new Mtval2Bundle) with TrapEntryMEventSinkBundle)
     .setAddr(CSRs.mtval2)
 
   val mseccfg = Module(new CSRModule("Mseccfg", new CSRBundle {
@@ -309,7 +309,7 @@ trait MachineLevel { self: NewCSR =>
   }).setAddr(CSRs.minstret)
 
   val mhpmcounters: Seq[CSRModule[_]] = (3 to 0x1F).map(num =>
-    Module(new CSRModule(s"Mhpmcounter$num") with HasMachineCounterControlBundle with HasPerfCounterBundle {
+    Module(new CSRModule(s"Mhpmcounter$num", new MhpmcounterBundle) with HasMachineCounterControlBundle with HasPerfCounterBundle {
       val countingInhibit = mcountinhibit.asUInt(num) | !countingEn
       val counterAdd = reg.ALL.asUInt +& perf.value
       when (w.wen) {
@@ -347,7 +347,9 @@ trait MachineLevel { self: NewCSR =>
   })
     .setAddr(CSRs.mhartid)
 
-  val mconfigptr = Module(new CSRModule("Mconfigptr"))
+  val mconfigptr = Module(new CSRModule("Mconfigptr", new CSRBundle {
+    val ALL = RO(63, 0)
+  }))
     .setAddr(CSRs.mconfigptr)
 
   val mstateen0 = Module(new CSRModule("Mstateen", new MstateenBundle0)).setAddr(CSRs.mstateen0)
@@ -556,15 +558,10 @@ class MvipBundle extends InterruptPendingBundle {
   this.getLocal.foreach(_.setRW().withReset(0.U))
 }
 
-class McauseBundle extends CauseBundle {
-  this.Interrupt.withReset(0.U)
-  this.ExceptionCode.withReset(0.U)
-}
-
 class Epc extends CSRBundle {
   import CSRConfig._
 
-  val epc = RW(VaddrMaxWidth - 1, 1)
+  val epc = RW(VaddrMaxWidth - 1, 1).withReset(0.U)
 }
 
 class McountinhibitBundle extends CSRBundle {
@@ -573,6 +570,10 @@ class McountinhibitBundle extends CSRBundle {
   val HPM3 = RW(31, 3).withReset(0.U)
 }
 
+class Mtval2Bundle extends FieldInitBundle
+
+class MhpmcounterBundle extends FieldInitBundle
+
 // todo: for the future, delete bypass between mhpmevents and perfEvents
 class MhpmeventBundle extends CSRBundle {
   val OF    = RW(63).withReset(0.U)

src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala

@@ -81,7 +81,7 @@ trait SupervisorLevel { self: NewCSR with MachineLevel =>
   val scause = Module(new CSRModule("Scause", new CauseBundle) with TrapEntryHSEventSinkBundle)
     .setAddr(CSRs.scause)
 
-  val stval = Module(new CSRModule("Stval") with TrapEntryHSEventSinkBundle)
+  val stval = Module(new CSRModule("Stval", new XtvalBundle) with TrapEntryHSEventSinkBundle)
     .setAddr(CSRs.stval)
 
   val sip = Module(new CSRModule("Sip", new SipBundle)
@@ -205,20 +205,20 @@ trait SupervisorLevel { self: NewCSR with MachineLevel =>
 class SstatusBundle extends CSRBundle {
   val SIE  = CSRWARLField   (1, wNoFilter)
   val SPIE = CSRWARLField   (5, wNoFilter)
-  val UBE  = CSRROField     (6)
-  val SPP  = CSRWARLField   (8, wNoFilter)
-  val VS   = ContextStatus  (10, 9)
-  val FS   = ContextStatus  (14, 13)
+  val UBE  = CSRROField     (6).withReset(0.U)
+  val SPP  = CSRWARLField   (8, wNoFilter).withReset(0.U)
+  val VS   = ContextStatus  (10, 9).withReset(ContextStatus.Off)
+  val FS   = ContextStatus  (14, 13).withReset(ContextStatus.Off)
   val XS   = ContextStatusRO(16, 15).withReset(0.U)
-  val SUM  = CSRWARLField   (18, wNoFilter)
-  val MXR  = CSRWARLField   (19, wNoFilter)
+  val SUM  = CSRWARLField   (18, wNoFilter).withReset(0.U)
+  val MXR  = CSRWARLField   (19, wNoFilter).withReset(0.U)
   val UXL  = XLENField      (33, 32).withReset(XLENField.XLEN64)
   val SD   = CSRROField     (63, (_, _) => FS === ContextStatus.Dirty || VS === ContextStatus.Dirty)
 }
 
 class SieBundle extends InterruptEnableBundle {
   this.getHS.foreach(_.setRW().withReset(0.U))
-  this.STIE.setRO()
+  this.STIE.setRO().withReset(0.U)
   this.getLocal.foreach(_.setRW().withReset(0.U))
   this.getM .foreach(_.setHardWired(0.U))
   this.getVS.foreach(_.setHardWired(0.U))
@@ -236,9 +236,9 @@ class SatpBundle extends CSRBundle {
   val MODE = SatpMode(63, 60, null).withReset(SatpMode.Bare)
   // WARL in privileged spec.
   // RW, since we support max width of ASID
-  val ASID = RW(44 - 1 + ASIDLEN, 44)
+  val ASID = RW(44 - 1 + ASIDLEN, 44).withReset(0.U)
   // Do WARL in SatpModule/VSatpModule
-  val PPN  = RW(43, 0)
+  val PPN  = RW(43, 0).withReset(0.U)
 }
 
 class SEnvCfg extends EnvCfg

src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala

@@ -145,7 +145,7 @@ trait Unprivileged { self: NewCSR with MachineLevel with SupervisorLevel =>
 
   val hpmcounters: Seq[CSRModule[_]] = (3 to 0x1F).map(num =>
     Module(new CSRModule(s"Hpmcounter$num", new CSRBundle {
-      val hpmcounter = RO(63, 0)
+      val hpmcounter = RO(63, 0).withReset(0.U)
     }) with HasMHPMSink {
       regOut.hpmcounter := mHPM.hpmcounters(num - 3)
     }).setAddr(CSRs.cycle + num)

src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala

@@ -132,7 +132,7 @@ trait VirtualSupervisorLevel { self: NewCSR with SupervisorLevel with Hypervisor
 
   // Todo: shrink the width of vstval to the maximum width Virtual Address
   val vstval = Module(
-    new CSRModule("VStval")
+    new CSRModule("VStval", new XtvalBundle)
       with TrapEntryVSEventSinkBundle
   )
     .setAddr(CSRs.vstval)
@@ -264,7 +264,7 @@ class VSipBundle extends InterruptPendingBundle {
 }
 
 class VSieBundle extends InterruptEnableBundle {
-  this.getLocal.foreach(_.setRW())
+  this.getLocal.foreach(_.setRW().withReset(0.U))
   this.getM .foreach(_.setHardWired(0.U))
   this.getVS.foreach(_.setHardWired(0.U))
   this.SGEIE.setHardWired(0.U)