power(IssueQueue): add clock gate for deqDelay reg (OpenXiangShan#3583)

rezado · Sep 18, 2024 · 52fc0c9 · 52fc0c9
1 parent b7dc2d1
commit 52fc0c9
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Showing 2 changed files with 16 additions and 3 deletions.
diff --git a/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala b/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
@@ -350,6 +350,10 @@ case class IssueBlockParams(
     MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x))))
   }
 
+  def genIssueValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIssueBundle]] = {
+    MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => ValidIO(new IssueQueueIssueBundle(this, x))))
+  }
+
   def genWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = {
     val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match {
       case IntScheduler() | MemScheduler() => needWakeupFromIntWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq

diff --git a/src/main/scala/xiangshan/backend/issue/IssueQueue.scala b/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
@@ -770,12 +770,21 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
     deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
   }
 
-  io.deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) =>
-    deqDly.valid := RegNext(deq.valid)
-    deqDly.bits := RegNext(deq.bits)
+  val deqDelay = Reg(params.genIssueValidBundle)
+  deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) =>
+    deqDly.valid := deq.valid
+    when(validVec.asUInt.orR) {
+      deqDly.bits := deq.bits
+    }
+    // deqBeforeDly.ready is always true
     deq.ready := true.B
   }
+  io.deqDelay.zip(deqDelay).foreach { case (sink, source) =>
+    sink.valid := source.valid
+    sink.bits := source.bits
+  }
   if(backendParams.debugEn) {
+    dontTouch(deqDelay)
     dontTouch(io.deqDelay)
     dontTouch(deqBeforeDly)
   }