build: purge chisel 3 and add deprecation check (OpenXiangShan#3250)

rezado · Jul 22, 2024 · e3da8ba · e3da8ba
1 parent 1b353ff
commit e3da8ba
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Showing 66 changed files with 435 additions and 805 deletions.
diff --git a/.github/workflows/emu.yml b/.github/workflows/emu.yml
@@ -62,22 +62,22 @@ jobs:
           make clean
       - name: generate XSNoCTop verilog file
         run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --generate --config XSNoCTopConfig --mfc
+          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --generate --config XSNoCTopConfig
       - name: check XSNoCTop verilog
         run: |
           python3 $GITHUB_WORKSPACE/.github/workflows/check_verilog.py build/rtl
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
       - name: generate verilog file
         run:
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --generate --num-cores 2 --mfc
+          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --generate --num-cores 2
       - name: check verilog
         run: |
           python3 $GITHUB_WORKSPACE/.github/workflows/check_verilog.py build/rtl
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
       - name: build MinimalConfig Release emu
         run: |
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \
-            --threads 8 --config MinimalConfig --release --mfc
+            --threads 8 --config MinimalConfig --release
       - name: run MinimalConfig - Linux
         run: |
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --numa --ci linux-hello-opensbi 2> perf.log
@@ -109,7 +109,7 @@ jobs:
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
       - name: Build EMU
         run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --build --threads 16 --mfc \
+          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --build --threads 16 \
             --pgo $GITHUB_WORKSPACE/ready-to-run/coremark-2-iteration.bin --llvm-profdata llvm-profdata
       - name: Basic Test - cputest
         run: |
@@ -164,7 +164,7 @@ jobs:
       - name: build KunminghuV2Config Release emu
         run: |
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \
-            --threads 8 --config KunminghuV2Config --release --mfc
+            --threads 8 --config KunminghuV2Config --release
       - name: run KunminghuV2Config - Linux
         run: |
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --numa --ci linux-hello-opensbi 2> perf.log
@@ -198,7 +198,7 @@ jobs:
         run: |
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \
             --dramsim3 /nfs/home/share/ci-workloads/DRAMsim3            \
-            --with-dramsim3 --threads 16 --mfc \
+            --with-dramsim3 --threads 16 \
             --pgo $GITHUB_WORKSPACE/ready-to-run/coremark-2-iteration.bin --llvm-profdata llvm-profdata
       - name: SPEC06 Test - mcf
         run: |
@@ -265,7 +265,7 @@ jobs:
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \
             --num-cores 2 --emu-optimize "" \
             --dramsim3 /nfs/home/share/ci-workloads/DRAMsim3 \
-            --with-dramsim3 --threads 16 --mfc \
+            --with-dramsim3 --threads 16 \
             --pgo $GITHUB_WORKSPACE/ready-to-run/coremark-2-iteration.bin --llvm-profdata llvm-profdata
       - name: MC Test
         run: |
@@ -302,7 +302,7 @@ jobs:
           ssh -tt eda01 "echo test-ok"
       - name: Generate Verilog for VCS
         run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --vcs-gen --no-db --xprop --mfc
+          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --vcs-gen --no-db --xprop
       - name: Build SIMV on Remote
         run: |
           ssh -tt eda01 "python3 `echo $GITHUB_WORKSPACE`/scripts/xiangshan.py --vcs-build --no-db --xprop"

diff --git a/.github/workflows/nightly.yml b/.github/workflows/nightly.yml
@@ -33,7 +33,7 @@ jobs:
         run: |
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build          \
             --dramsim3 /nfs/home/share/ci-workloads/DRAMsim3              \
-            --with-dramsim3 --threads 16 --spike --mfc                    \
+            --with-dramsim3 --threads 16 --spike                          \
             --pgo $GITHUB_WORKSPACE/ready-to-run/coremark-2-iteration.bin \
             --llvm-profdata llvm-profdata
       - name: Random Checkpoint 0

diff --git a/Makefile b/Makefile
@@ -36,7 +36,6 @@ MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
 
 CONFIG ?= DefaultConfig
 NUM_CORES ?= 1
-MFC ?= 1
 
 ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),)
 $(error At most one target can be specified)
@@ -49,20 +48,13 @@ GOALS = $(MAKECMDGOALS)
 endif
 
 # common chisel args
-ifeq ($(MFC),1)
-CHISEL_VERSION = chisel
 FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf"
 SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf"
 MFC_ARGS = --dump-fir --target systemverilog --split-verilog \
            --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none"
 RELEASE_ARGS += $(MFC_ARGS)
 DEBUG_ARGS += $(MFC_ARGS)
 PLDM_ARGS += $(MFC_ARGS)
-else
-CHISEL_VERSION = chisel3
-FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
-SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
-endif
 
 ifneq ($(XSTOP_PREFIX),)
 RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX)
@@ -140,16 +132,14 @@ endif
 .DEFAULT_GOAL = verilog
 
 help:
-	mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help
+	mill -i xiangshan.runMain $(FPGATOP) --help
 
 $(TOP_V): $(SCALA_FILE)
 	mkdir -p $(@D)
-	$(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP)   \
+	$(TIME_CMD) mill -i xiangshan.runMain $(FPGATOP)   \
 		--target-dir $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS)        \
 		--num-cores $(NUM_CORES) $(RELEASE_ARGS)
-ifeq ($(MFC),1)
 	$(MEM_GEN_SEP) "$(MEM_GEN)" "$@.conf" "$(@D)"
-endif
 	@git log -n 1 >> .__head__
 	@git diff >> .__diff__
 	@sed -i 's/^/\/\// ' .__head__
@@ -164,12 +154,10 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	mkdir -p $(@D)
 	@echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG)
 	@date -R | tee -a $(TIMELOG)
-	$(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP)    \
+	$(TIME_CMD) mill -i xiangshan.test.runMain $(SIMTOP)    \
 		--target-dir $(@D) --config $(CONFIG) $(SIM_MEM_ARGS)              \
 		--num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace
-ifeq ($(MFC),1)
 	$(MEM_GEN_SEP) "$(MEM_GEN)" "$@.conf" "$(@D)"
-endif
 	@git log -n 1 >> .__head__
 	@git diff >> .__diff__
 	@sed -i 's/^/\/\// ' .__head__
@@ -187,9 +175,7 @@ else
 	sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX)
 endif
 endif
-ifeq ($(MFC),1)
 	sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX)
-endif
 
 sim-verilog: $(SIM_TOP_V)
 
@@ -208,7 +194,7 @@ bsp:
 	mill -i mill.bsp.BSP/install
 
 idea:
-	mill -i mill.scalalib.GenIdea/idea
+	mill -i mill.idea.GenIdea/idea
 
 # verilator simulation
 emu: sim-verilog