Merge branch 'main' into dhower-qc-patch-1

Rakefile

@@ -33,8 +33,8 @@ def cfg_arch_for(config_name)
     )
 end
 
-file "#{$root}/.stamps/dev_gems" do |t|
-  sh "bundle exec yard config --gem-install-yri"
+file "#{$root}/.stamps/dev_gems" => ["#{$root}/.stamps"] do |t|
+  #sh "bundle exec yard config --gem-install-yri"
   sh "bundle exec yard gem"
   FileUtils.touch t.name
 end

arch/ext/Zcd.yaml

@@ -0,0 +1,43 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zcd
+long_name: Compressed instructions for double precision floating point
+description: |
+  Zcd is the existing set of compressed double precision floating point loads and stores:
+  `c.fld`, `c.fldsp`, `c.fsd`, `c.fsdsp`.
+
+type: unprivileged
+company:
+  name: RISC-V International
+  url: https://riscv.org
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: 2023-04
+    repositories:
+      - url: https://github.com/riscv/riscv-code-size-reduction
+        branch: main
+    contributors:
+      - name: Tariq Kurd
+      - name: Ibrahim Abu Kharmeh
+      - name: Torbjørn Viem Ness
+      - name: Matteo Perotti
+      - name: Nidal Faour
+      - name: Bill Traynor
+      - name: Rafael Sene
+      - name: Xinlong Wu
+      - name: sinan
+      - name: Jeremy Bennett
+      - name: Heda Chen
+      - name: Alasdair Armstrong
+      - name: Graeme Smecher
+      - name: Nicolas Brunie
+      - name: Jiawei
+    requires:
+      allOf:
+        - anyOf:
+          - { name: Zca, version: "= 1.0.0" }
+          - { name: C, version: "= 1.0.0" }
+        - { name: D, version: "~> 2.2.0" }

arch/inst/F/fadd.s.yaml

@@ -3,9 +3,10 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fadd.s
-long_name: No synopsis available.
+long_name: Single-precision floating-point addition
 description: |
-  No description available.
+  Do the single-precision floating-point addition of fs1 and fs2 and store the result in fd.
+  rm is the dynamic Rounding Mode.
 definedBy: F
 assembly: fd, fs1, fs2, rm
 encoding:

arch/inst/F/fleq.s.yaml

@@ -6,7 +6,7 @@ name: fleq.s
 long_name: No synopsis available.
 description: |
   No description available.
-definedBy: { allOf: [F, Zfa] }
+definedBy: Zfa
 assembly: xd, fs1, fs2
 encoding:
   match: 1010000----------100-----1010011

arch/inst/F/fli.s.yaml

@@ -6,7 +6,7 @@ name: fli.s
 long_name: No synopsis available.
 description: |
   No description available.
-definedBy: { allOf: [F, Zfa] }
+definedBy: Zfa
 assembly: fd, fs1
 encoding:
   match: 111100000001-----000-----1010011

arch/inst/F/fltq.s.yaml

@@ -6,7 +6,7 @@ name: fltq.s
 long_name: No synopsis available.
 description: |
   No description available.
-definedBy: { allOf: [F, Zfa] }
+definedBy: Zfa
 assembly: xd, fs1, fs2
 encoding:
   match: 1010000----------101-----1010011

arch/inst/F/fmaxm.s.yaml

@@ -6,7 +6,7 @@ name: fmaxm.s
 long_name: No synopsis available.
 description: |
   No description available.
-definedBy: { allOf: [F, Zfa] }
+definedBy: Zfa
 assembly: xd, xs1, xs2
 encoding:
   match: 0010100----------011-----1010011

arch/inst/F/fminm.s.yaml

@@ -6,7 +6,7 @@ name: fminm.s
 long_name: No synopsis available.
 description: |
   No description available.
-definedBy: { allOf: [F, Zfa] }
+definedBy: Zfa
 assembly: fd, fs1, fs2
 encoding:
   match: 0010100----------010-----1010011

arch/inst/F/fround.s.yaml

@@ -6,7 +6,7 @@ name: fround.s
 long_name: No synopsis available.
 description: |
   No description available.
-definedBy: { allOf: [F, Zfa] }
+definedBy: Zfa
 assembly: fd, xs1, rm
 encoding:
   match: 010000000100-------------1010011

arch/inst/F/froundnx.s.yaml

@@ -6,7 +6,7 @@ name: froundnx.s
 long_name: No synopsis available.
 description: |
   No description available.
-definedBy: { allOf: [F, Zfa] }
+definedBy: Zfa
 assembly: fd, rs1, rm
 encoding:
   match: 010000000101-------------1010011

arch/inst/F/fsub.s.yaml

@@ -3,9 +3,10 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fsub.s
-long_name: No synopsis available.
+long_name: Single-precision floating-point subtraction
 description: |
-  No description available.
+  Do the single-precision floating-point subtraction of fs2 from fs1 and store the result in fd.
+  rm is the dynamic Rounding Mode.
 definedBy: F
 assembly: fd, fs1, fs2, rm
 encoding:
@@ -26,7 +27,8 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-
+  RoundingMode mode = rm_to_mode(X[rm], $encoding);
+  X[fd] = f32_sub(X[fs1], X[fs2], mode);
 sail(): |
   {
     let rs1_val_32b = F_or_X_S(rs1);

arch/inst/Zbkb/brev8.yaml

@@ -3,11 +3,10 @@
 $schema: inst_schema.json#
 kind: instruction
 name: brev8
-long_name: No synopsis available.
+long_name: Reverse bits in bytes
 description: |
-  No description available.
-definedBy:
-  anyOf: [B, Zbkb, Zk, Zkn, Zks]
+  This instruction reverses the order of the bits in every byte of a register.
+definedBy: Zbkb
 assembly: xd, xs1
 encoding:
   match: 011010000111-----101-----0010011
@@ -23,3 +22,20 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg input = X[rs1];
+  XReg output = 0;
+
+  for(U32 i=0; i<(xlen()-8); i = i+8) {
+    for(U32 j=0; j<8; j = j+1) {
+      output[(i*8)+(7-j)] = input[(i*8)+j];
+    }
+  }
+
+  X[rd] = output;
+
+sail(): |
+  result : xlenbits = EXTZ(0b0);
+  foreach (i from 0 to sizeof(xlen) by 8) {
+    result[i+7..i] = reverse_bits_in_byte(X(rs1)[i+7..i]);
+  };
+  X(rd) = result;

arch/inst/Zbkb/unzip.yaml

@@ -3,11 +3,12 @@
 $schema: inst_schema.json#
 kind: instruction
 name: unzip
-long_name: No synopsis available.
+long_name: Bit deinterleave
 description: |
-  No description available.
-definedBy:
-  anyOf: [B, Zbkb, Zk, Zkn, Zks]
+  This instruction gathers bits from the high and low halves of the source word into odd/even bit
+  positions in the destination word. It is the inverse of the zip instruction. This instruction is
+  available only on RV32.
+definedBy: Zbkb
 assembly: xd, xs1
 encoding:
   match: 000010001111-----101-----0010011
@@ -24,3 +25,18 @@ access:
 data_independent_timing: false
 base: 32
 operation(): |
+  XReg input = X[rs1];
+  XReg output = 0;
+
+  for(U32 i=0; i<(xlen()/2-1); i = i+1) {
+    output[i] = input[2*i];
+    output[i+xlen()/2] = input[2*i+1];
+  }
+
+  X[rd] = output;
+
+sail(): |
+  foreach (i from 0 to xlen/2-1) {
+    X(rd)[i] = X(rs1)[2*i];
+    X(rd)[i+xlen/2] = X(rs1)[2*i+1];
+  }