Significant refactoring.

- 1stage, 3stage supervisor mode improved - significant bug fixes re: CSR file interfacing - added uarch counters - 1stage, 2stage datapath improved - removed vestigial RISC-V v1.0 logic
rkzai · Aug 30, 2014 · 88007f6 · 88007f6
1 parent 1b4e15b
commit 88007f6
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Showing 37 changed files with 701 additions and 649 deletions.
diff --git a/Makefile.in b/Makefile.in
@@ -8,8 +8,7 @@
 # Many different processors are provided. To switch between which processor(s)
 # you would like to build, simply set the $(targets) variable as appropriate. 
 
-#all_targets := rv32_1stage rv32_2stage rv32_3stage rv32_5stage rv32_ucode
-all_targets := rv32_1stage rv32_2stage rv32_5stage rv32_ucode
+all_targets := rv32_1stage rv32_2stage rv32_3stage rv32_5stage rv32_ucode
 targets     := $(all_targets)
 
 # To switch between which processor the Makefile would like to build, it will

diff --git a/emulator/common/htif_emulator.cc b/emulator/common/htif_emulator.cc
@@ -10,43 +10,43 @@
 // or waiting on the chip (target). 
 
 void htif_emulator_t::tick(
-   bool pcr_req_ready,
+   bool csr_req_ready,
    bool mem_req_ready,
 
-   bool pcr_rep_valid,
-   uint64_t pcr_rep_bits,
+   bool csr_rep_valid,
+   uint64_t csr_rep_bits,
 
    bool mem_rep_valid,
    uint64_t mem_rep_bits
    )
 {
 
    // default outputs 
-   pcr_rep_ready = true;
+   csr_rep_ready = true;
 
-   pcr_req_valid = false;
-   pcr_req_bits_addr = 0;
-   pcr_req_bits_data = 0;
-   pcr_req_bits_rw = false;
+   csr_req_valid = false;
+   csr_req_bits_addr = 0;
+   csr_req_bits_data = 0;
+   csr_req_bits_rw = false;
 
    mem_req_valid = false;
    mem_req_bits_addr = 0;
    mem_req_bits_data = 0;
    mem_req_bits_rw = false;
 
    // if we receive a response back from the chip, send it to the fesvr
-   if (pcr_rep_valid)
+   if (csr_rep_valid)
    {
-      //fprintf(stderr, "\n\tPCR reply VALID, data: %lx\n\n", pcr_rep_bits);
+      //fprintf(stderr, "\n\tcsr reply VALID, data: %lx\n\n", csr_rep_bits);
       packet_header_t ack(HTIF_CMD_ACK, seqno, 1, 0);
       send(&ack, sizeof(ack));
-      send(&pcr_rep_bits, sizeof(pcr_rep_bits));
+      send(&csr_rep_bits, sizeof(csr_rep_bits));
 
       state = PENDING_HOST;
    }
    if (mem_rep_valid)
    {
-      //fprintf(stderr, "\n\tmem reply VALID, data: %lx\n\n", pcr_rep_bits);
+      //fprintf(stderr, "\n\tmem reply VALID, data: %lx\n\n", csr_rep_bits);
       packet_header_t ack(HTIF_CMD_ACK, seqno, 1, 0);
       send(&ack, sizeof(ack));
       send(&mem_rep_bits, sizeof(mem_rep_bits));
@@ -166,10 +166,10 @@ void htif_emulator_t::tick(
          }
          else
          {
-            pcr_req_valid = true;
-            pcr_req_bits_addr = regno;
-            pcr_req_bits_data = new_val;
-            pcr_req_bits_rw = (hdr.cmd == HTIF_CMD_WRITE_CONTROL_REG);
+            csr_req_valid = true;
+            csr_req_bits_addr = regno;
+            csr_req_bits_data = new_val;
+            csr_req_bits_rw = (hdr.cmd == HTIF_CMD_WRITE_CONTROL_REG);
 
             state = PENDING_TARGET;
          }

diff --git a/emulator/common/htif_emulator.h b/emulator/common/htif_emulator.h
@@ -35,24 +35,24 @@ class htif_emulator_t : public htif_pthread_t
    void tick                
    (
       // these are inputs into the htif, from the testharness
-      bool pcr_req_ready,
+      bool csr_req_ready,
       bool mem_req_ready,
 
-      bool pcr_rep_valid,
-      uint64_t pcr_rep_bits,
+      bool csr_rep_valid,
+      uint64_t csr_rep_bits,
 
       bool mem_rep_valid,
       uint64_t mem_rep_bits
    );         
 
    // Inputs to the design under test
    bool     reset; // visible to the core (allow us to initialize memory)
-   bool     pcr_rep_ready;
+   bool     csr_rep_ready;
 
-   bool     pcr_req_valid;
-   uint64_t pcr_req_bits_addr;
-   uint64_t pcr_req_bits_data;
-   bool     pcr_req_bits_rw;
+   bool     csr_req_valid;
+   uint64_t csr_req_bits_addr;
+   uint64_t csr_req_bits_data;
+   bool     csr_req_bits_rw;
 
    bool     mem_req_valid;
    uint64_t mem_req_bits_addr;

diff --git a/emulator/rv32_1stage/emulator.cpp b/emulator/rv32_1stage/emulator.cpp
@@ -118,7 +118,7 @@ int main(int argc, char** argv)
 
    // i'm using uint64_t for these variables, so they shouldn't be larger
    // (also consequences all the way to the Chisel memory)
-   assert (dut.Top__io_htif_pcr_rep_bits.width() <= 64);
+   assert (dut.Top__io_htif_csr_rep_bits.width() <= 64);
    assert (dut.Top__io_htif_mem_rep_bits.width() <= 64);  
 
 //  int htif_bits = dut.Top__io_host_in_bits.width();
@@ -142,23 +142,23 @@ int main(int argc, char** argv)
       // perform all fesvr HostIO to HTIFIO transformations in software
       htif->tick(
          // from tile to me,the testharness
-           dut.Top__io_htif_pcr_req_ready.lo_word()
+           dut.Top__io_htif_csr_req_ready.lo_word()
          , dut.Top__io_htif_mem_req_ready.lo_word()
 
-         , dut.Top__io_htif_pcr_rep_valid.lo_word()
-         , dut.Top__io_htif_pcr_rep_bits.lo_word()
+         , dut.Top__io_htif_csr_rep_valid.lo_word()
+         , dut.Top__io_htif_csr_rep_bits.lo_word()
 
          , dut.Top__io_htif_mem_rep_valid.lo_word()
          , dut.Top__io_htif_mem_rep_bits.lo_word()
       );
 
       // send HTIF signals to the chip
-      dut.Top__io_htif_pcr_rep_ready = htif->pcr_rep_ready;
+      dut.Top__io_htif_csr_rep_ready = htif->csr_rep_ready;
 
-      dut.Top__io_htif_pcr_req_valid = htif->pcr_req_valid;
-      dut.Top__io_htif_pcr_req_bits_data = htif->pcr_req_bits_data;
-      dut.Top__io_htif_pcr_req_bits_addr = htif->pcr_req_bits_addr;
-      dut.Top__io_htif_pcr_req_bits_rw = htif->pcr_req_bits_rw;
+      dut.Top__io_htif_csr_req_valid = htif->csr_req_valid;
+      dut.Top__io_htif_csr_req_bits_data = htif->csr_req_bits_data;
+      dut.Top__io_htif_csr_req_bits_addr = htif->csr_req_bits_addr;
+      dut.Top__io_htif_csr_req_bits_rw = htif->csr_req_bits_rw;
 
       dut.Top__io_htif_mem_req_valid = htif->mem_req_valid;
       dut.Top__io_htif_mem_req_bits_addr = htif->mem_req_bits_addr;

diff --git a/emulator/rv32_2stage/emulator.cpp b/emulator/rv32_2stage/emulator.cpp
@@ -57,8 +57,8 @@ int main(int argc, char** argv)
       vcdfile = strcmp(vcd, "-") == 0 ? stdout : fopen(vcd, "w");
       assert(vcdfile);
       fprintf(vcdfile, "$scope module Testbench $end\n");
-      fprintf(vcdfile, "$var reg %d NDISASM instruction $end\n", disasm_len*8);
-      fprintf(vcdfile, "$var reg 64 NCYCLE cycle $end\n");
+      //fprintf(vcdfile, "$var reg %d NDISASM instruction $end\n", disasm_len*8);
+      //fprintf(vcdfile, "$var reg 64 NCYCLE cycle $end\n");
       fprintf(vcdfile, "$upscope $end\n");
    }
 
@@ -121,7 +121,7 @@ int main(int argc, char** argv)
 
    // i'm using uint64_t for these variables, so they shouldn't be larger
    // (also consequences all the way to the Chisel memory)
-   assert (dut.Top__io_htif_pcr_rep_bits.width() <= 64);
+   assert (dut.Top__io_htif_csr_rep_bits.width() <= 64);
    assert (dut.Top__io_htif_mem_rep_bits.width() <= 64);  
 
 //  int htif_bits = dut.Top__io_host_in_bits.width();
@@ -145,23 +145,23 @@ int main(int argc, char** argv)
       // perform all fesvr HostIO to HTIFIO transformations in software
       htif->tick(
          // from tile to me,the testharness
-           dut.Top__io_htif_pcr_req_ready.lo_word()
+           dut.Top__io_htif_csr_req_ready.lo_word()
          , dut.Top__io_htif_mem_req_ready.lo_word()
 
-         , dut.Top__io_htif_pcr_rep_valid.lo_word()
-         , dut.Top__io_htif_pcr_rep_bits.lo_word()
+         , dut.Top__io_htif_csr_rep_valid.lo_word()
+         , dut.Top__io_htif_csr_rep_bits.lo_word()
 
          , dut.Top__io_htif_mem_rep_valid.lo_word()
          , dut.Top__io_htif_mem_rep_bits.lo_word()
       );
 
       // send HTIF signals to the chip
-      dut.Top__io_htif_pcr_rep_ready = htif->pcr_rep_ready;
+      dut.Top__io_htif_csr_rep_ready = htif->csr_rep_ready;
 
-      dut.Top__io_htif_pcr_req_valid = htif->pcr_req_valid;
-      dut.Top__io_htif_pcr_req_bits_data = htif->pcr_req_bits_data;
-      dut.Top__io_htif_pcr_req_bits_addr = htif->pcr_req_bits_addr;
-      dut.Top__io_htif_pcr_req_bits_rw = htif->pcr_req_bits_rw;
+      dut.Top__io_htif_csr_req_valid = htif->csr_req_valid;
+      dut.Top__io_htif_csr_req_bits_data = htif->csr_req_bits_data;
+      dut.Top__io_htif_csr_req_bits_addr = htif->csr_req_bits_addr;
+      dut.Top__io_htif_csr_req_bits_rw = htif->csr_req_bits_rw;
 
       dut.Top__io_htif_mem_req_valid = htif->mem_req_valid;
       dut.Top__io_htif_mem_req_bits_addr = htif->mem_req_bits_addr;

diff --git a/emulator/rv32_3stage/emulator.cpp b/emulator/rv32_3stage/emulator.cpp
@@ -56,7 +56,6 @@ int main(int argc, char** argv)
       vcdfile = strcmp(vcd, "-") == 0 ? stdout : fopen(vcd, "w");
       assert(vcdfile);
       fprintf(vcdfile, "$scope module Testbench $end\n");
-      fprintf(vcdfile, "$var reg %d NDISASM instruction $end\n", disasm_len*8);
       fprintf(vcdfile, "$var reg 64 NCYCLE cycle $end\n");
       fprintf(vcdfile, "$upscope $end\n");
    }
@@ -116,7 +115,7 @@ int main(int argc, char** argv)
 
    // i'm using uint64_t for these variables, so they shouldn't be larger
    // (also consequences all the way to the Chisel memory)
-   assert (dut.Top__io_htif_pcr_rep_bits.width() <= 64);
+   assert (dut.Top__io_htif_csr_rep_bits.width() <= 64);
    assert (dut.Top__io_htif_mem_rep_bits.width() <= 64);  
 
 //  int htif_bits = dut.Top__io_host_in_bits.width();
@@ -140,23 +139,23 @@ int main(int argc, char** argv)
       // perform all fesvr HostIO to HTIFIO transformations in software
       htif->tick(
          // from tile to me,the testharness
-           dut.Top__io_htif_pcr_req_ready.lo_word()
+           dut.Top__io_htif_csr_req_ready.lo_word()
          , dut.Top__io_htif_mem_req_ready.lo_word()
 
-         , dut.Top__io_htif_pcr_rep_valid.lo_word()
-         , dut.Top__io_htif_pcr_rep_bits.lo_word()
+         , dut.Top__io_htif_csr_rep_valid.lo_word()
+         , dut.Top__io_htif_csr_rep_bits.lo_word()
 
          , dut.Top__io_htif_mem_rep_valid.lo_word()
          , dut.Top__io_htif_mem_rep_bits.lo_word()
       );
 
       // send HTIF signals to the chip
-      dut.Top__io_htif_pcr_rep_ready = htif->pcr_rep_ready;
+      dut.Top__io_htif_csr_rep_ready = htif->csr_rep_ready;
 
-      dut.Top__io_htif_pcr_req_valid = htif->pcr_req_valid;
-      dut.Top__io_htif_pcr_req_bits_data = htif->pcr_req_bits_data;
-      dut.Top__io_htif_pcr_req_bits_addr = htif->pcr_req_bits_addr;
-      dut.Top__io_htif_pcr_req_bits_rw = htif->pcr_req_bits_rw;
+      dut.Top__io_htif_csr_req_valid = htif->csr_req_valid;
+      dut.Top__io_htif_csr_req_bits_data = htif->csr_req_bits_data;
+      dut.Top__io_htif_csr_req_bits_addr = htif->csr_req_bits_addr;
+      dut.Top__io_htif_csr_req_bits_rw = htif->csr_req_bits_rw;
 
       dut.Top__io_htif_mem_req_valid = htif->mem_req_valid;
       dut.Top__io_htif_mem_req_bits_addr = htif->mem_req_bits_addr;
@@ -170,7 +169,11 @@ int main(int argc, char** argv)
         dut.print(logfile);
 
       if (vcd)
+      {
         dut.dump(vcdfile, trace_count);
+//        dat_dump(vcdfile, dat_t<64>(trace_count), trace_count);
+//        dat_dump(vcdfile, dat_t<64>(trace_count), val_t("NCYCLE\n"));
+      }
 
       dut.clock_hi(LIT<1>(0));
       trace_count++;

diff --git a/emulator/rv32_5stage/emulator.cpp b/emulator/rv32_5stage/emulator.cpp
@@ -116,7 +116,7 @@ int main(int argc, char** argv)
 
    // i'm using uint64_t for these variables, so they shouldn't be larger
    // (also consequences all the way to the Chisel memory)
-   assert (dut.Top__io_htif_pcr_rep_bits.width() <= 64);
+   assert (dut.Top__io_htif_csr_rep_bits.width() <= 64);
    assert (dut.Top__io_htif_mem_rep_bits.width() <= 64);  
 
 //  int htif_bits = dut.Top__io_host_in_bits.width();
@@ -140,23 +140,23 @@ int main(int argc, char** argv)
       // perform all fesvr HostIO to HTIFIO transformations in software
       htif->tick(
          // from tile to me,the testharness
-           dut.Top__io_htif_pcr_req_ready.lo_word()
+           dut.Top__io_htif_csr_req_ready.lo_word()
          , dut.Top__io_htif_mem_req_ready.lo_word()
 
-         , dut.Top__io_htif_pcr_rep_valid.lo_word()
-         , dut.Top__io_htif_pcr_rep_bits.lo_word()
+         , dut.Top__io_htif_csr_rep_valid.lo_word()
+         , dut.Top__io_htif_csr_rep_bits.lo_word()
 
          , dut.Top__io_htif_mem_rep_valid.lo_word()
          , dut.Top__io_htif_mem_rep_bits.lo_word()
       );
 
       // send HTIF signals to the chip
-      dut.Top__io_htif_pcr_rep_ready = htif->pcr_rep_ready;
+      dut.Top__io_htif_csr_rep_ready = htif->csr_rep_ready;
 
-      dut.Top__io_htif_pcr_req_valid = htif->pcr_req_valid;
-      dut.Top__io_htif_pcr_req_bits_data = htif->pcr_req_bits_data;
-      dut.Top__io_htif_pcr_req_bits_addr = htif->pcr_req_bits_addr;
-      dut.Top__io_htif_pcr_req_bits_rw = htif->pcr_req_bits_rw;
+      dut.Top__io_htif_csr_req_valid = htif->csr_req_valid;
+      dut.Top__io_htif_csr_req_bits_data = htif->csr_req_bits_data;
+      dut.Top__io_htif_csr_req_bits_addr = htif->csr_req_bits_addr;
+      dut.Top__io_htif_csr_req_bits_rw = htif->csr_req_bits_rw;
 
       dut.Top__io_htif_mem_req_valid = htif->mem_req_valid;
       dut.Top__io_htif_mem_req_bits_addr = htif->mem_req_bits_addr;

diff --git a/emulator/rv32_ucode/emulator.cpp b/emulator/rv32_ucode/emulator.cpp
@@ -118,7 +118,7 @@ int main(int argc, char** argv)
 
    // i'm using uint64_t for these variables, so they shouldn't be larger
    // (also consequences all the way to the Chisel memory)
-   assert (dut.Top__io_htif_pcr_rep_bits.width() <= 64);
+   assert (dut.Top__io_htif_csr_rep_bits.width() <= 64);
    assert (dut.Top__io_htif_mem_rep_bits.width() <= 64);  
 
 //  int htif_bits = dut.Top__io_host_in_bits.width();
@@ -142,23 +142,23 @@ int main(int argc, char** argv)
       // perform all fesvr HostIO to HTIFIO transformations in software
       htif->tick(
          // from tile to me,the testharness
-           dut.Top__io_htif_pcr_req_ready.lo_word()
+           dut.Top__io_htif_csr_req_ready.lo_word()
          , dut.Top__io_htif_mem_req_ready.lo_word()
 
-         , dut.Top__io_htif_pcr_rep_valid.lo_word()
-         , dut.Top__io_htif_pcr_rep_bits.lo_word()
+         , dut.Top__io_htif_csr_rep_valid.lo_word()
+         , dut.Top__io_htif_csr_rep_bits.lo_word()
 
          , dut.Top__io_htif_mem_rep_valid.lo_word()
          , dut.Top__io_htif_mem_rep_bits.lo_word()
       );
 
       // send HTIF signals to the chip
-      dut.Top__io_htif_pcr_rep_ready = htif->pcr_rep_ready;
+      dut.Top__io_htif_csr_rep_ready = htif->csr_rep_ready;
 
-      dut.Top__io_htif_pcr_req_valid = htif->pcr_req_valid;
-      dut.Top__io_htif_pcr_req_bits_data = htif->pcr_req_bits_data;
-      dut.Top__io_htif_pcr_req_bits_addr = htif->pcr_req_bits_addr;
-      dut.Top__io_htif_pcr_req_bits_rw = htif->pcr_req_bits_rw;
+      dut.Top__io_htif_csr_req_valid = htif->csr_req_valid;
+      dut.Top__io_htif_csr_req_bits_data = htif->csr_req_bits_data;
+      dut.Top__io_htif_csr_req_bits_addr = htif->csr_req_bits_addr;
+      dut.Top__io_htif_csr_req_bits_rw = htif->csr_req_bits_rw;
 
       dut.Top__io_htif_mem_req_valid = htif->mem_req_valid;
       dut.Top__io_htif_mem_req_bits_addr = htif->mem_req_bits_addr;

diff --git a/src/common/consts.scala b/src/common/consts.scala
@@ -5,13 +5,6 @@ package constants
 import Chisel._
 import scala.math._
 
-//trait InterruptConstants 
-//{
-//   val CAUSE_INTERRUPT = 32
-//   val IRQ_IPI = 5
-//   val IRQ_TIMER = 7
-//}
-
 trait RISCVConstants
 {
    val START_ADDR = 0x2000
@@ -31,7 +24,6 @@ trait RISCVConstants
    val SHAMT_5_BIT = 25
    val LONGEST_IMM_SZ = 20
    val X0 = UInt(0)
-   val RA = UInt(1) // return address register
 
    // The Bubble Instruction (Machine generated NOP)
    // Insert (XOR x0,x0,x0) which is different from software compiler 
@@ -44,19 +36,8 @@ trait RISCVConstants
 
 trait ExcCauseConstants
 {
-  // Exception Causes
-  // itlb == 1
+  // Extra Exception Causes (check instructions.scala)
   val EXC_CAUSE_SZ = 5
-  val EXCEPTION_ILLEGAL    = UInt(2, EXC_CAUSE_SZ)
-  val EXCEPTION_PRIVILEGED = UInt(3, EXC_CAUSE_SZ)
-  //fpu == 4
-  val EXCEPTION_SCALL    = UInt(6, EXC_CAUSE_SZ)
-  //ma ld == 8
-  //ma st == 9
-  //dtlb ld == 10
-  //dtlb st == 11
-  //xcpt_vec disabled == 12
-  //inst addr misaligned == 0
   val EXC_RETURN = UInt(31, EXC_CAUSE_SZ)
 }
 }