refactor: modify the comment related to the addend of FMA

Processor/Src/Pipeline/FPBackEnd/FPExecutionStage.sv

@@ -177,10 +177,18 @@ module FPExecutionStage(
             fmaMulLHS[i] = fpuCode[i] inside {FC_FNMSUB, FC_FNMADD} ? {~fuOpA[i].data[31], fuOpA[i].data[30:0]} : fuOpA[i].data;
             fmaMulRHS[i] = fpuCode[i] inside {FC_ADD, FC_SUB} ? 32'h3f800000 : fuOpB[i].data;
             if(fpuCode[i] == FC_MUL) begin
-                // Hack: set sign bit considering rounding mode
-                // +a * +0.0 should return +0.0 regardless of rounding mode,
-                // However, when implemented with fma(+a, +0.0, -0.0),
-                // it returns -0.0 when round_mode = 2
+                // If the arithmetical result is not zero, 
+                // adding either -0.0 or +0.0 will produce the same result as the multiplication result.
+                // If the arithmetical result is zero, 
+                // adding a zero with the same sign ensures that the result matches the multiplication result.
+                // Therefore, this approach is valid.
+                //
+                // Always adding +0.0 is incorrect: 
+                //   when the round_mode != 2 (downward) and the multiplication result is -0.0, 
+                //   the output will incorrectly become +0.0.
+                // Similarly, always adding -0.0 is also incorrect:
+                //   when the round_mode == 2 (downward) and the multiplication result is +0.0,
+                //   the output will incorrectly become -0.0.
                 fmaAddend[i] = { fmaMulLHS[i][31] ^ fmaMulRHS[i][31] , 31'h0 };
             end
             else if (fpuCode[i] == FC_ADD) begin