MIPS Simulator 👨‍💻

A simple non-pipelined 32-bit MIPS Simulator in Verilog

Install

git clone https://github.com/DaKeiser/mips.git

Dependencies

• iVerilog HDL.

• GTKWave.

  • Installation Guide for iverilog and GTKWave

Usage

~/mips$ iverilog mipsProcessor.v
~/mips$ ./a.out

Run tests

~/mips$ gtkwave mips.vcd

Description

We have created separate modules for fetch, decode, execute, memory and writeback operations.

• Instructions are given in the file fact.dat. To convert the instructions into 32-bit binary codes, use this.
• Dont forget to add 11111111111111111111111111111111 at the end of the set of instructions
• The value N for which the factorial must be found must be passed in it.
• Changes that you need to make once you gave a specified set of instructions:
  • Change the parameter instruction_count in fetch.v
  • Similarly change the parameter INSTRUCTION_COUNT in mipsProcessor.v
• Now run the following command iverilog mipsProcessor.v (You need to have iverilog and GTKWave installed)
• Then do an ./a.out
• And find the response to your instruction set in either registers.dat file or mainMemory.dat file (Changes happening depends on the type of instruction you give)
• In our premade fact.dat file our output is visible in registers.dat file in line number 20 or in mainMemory.dat in line number 3.
• If you want to see the number of cycles the instruction took, head over to GTKWave by running gtkwave mips.vcd and click on mipsTb -> mainModule
• Drag and drop clock and curInstruction[31:0]. You will get an estimate of the number of cycles it is taking.
• You can also check for any intermediate signal at any module to understand which signals are high or low in a particular instruction.

Preview

• Instructions are written here. We have implemented a code to find the factorial of 5.

• All changes in Registers are found here

• All the data in main memory is stored and written back here

• Check out the stages on how the instructions are executed here

Authors

👤 Sai Rithwik M

• Github: @DaKeiser

👤 Sama Sai Kartik

• Github: @Kartik-Sama

👤 Soham Joshi

• Github: @soham-joshi

📝 License

Copyright © 2019 Sai Rithwik M.
This project is MIT licensed. _