Verilog Memory Modules and Testbenches
Description
This project contains Verilog modules for various types of memory designs, including Single Port RAM, Dual Port RAM, and ROM, along with their respective testbenches for simulation and verification.
Modules
1.Single Port RAM (single_port_ram.v):
a. A simple RAM with 64x8-bit memory. b. Supports read and write operations on a single port.
- Dual Port RAM (dual_port_ram.v):
a. A RAM with 64x8-bit memory. b. Supports simultaneous read/write operations on two ports.
- ROM (rom.v):
a. A ROM with 16x4-bit memory. b. Outputs pre-stored data based on the address input.
Testbenches
- Single Port RAM Testbench (single_port_ram_tb.v):
a. Initializes clock and stimulus. b. Verifies read and write operations by observing the output.
- Dual Port RAM Testbench (dual_port_ram_tb.v):
a.Initializes clock and stimulus. b.Verifies simultaneous read/write operations on both ports.
- ROM Testbench (rom_tb.v):
a. Initializes clock and stimulus. b. Verifies ROM outputs based on various addresses and enable signals.
Usage
Simulation:
- Compile and simulate the Verilog files using a simulator like ModelSim or Vivado.
- Use the testbenches to verify functionality.
- Observe the waveforms using the generated VCD files.
Compilation:
- Ensure the main modules and testbenches are in the same directory.
- Run the testbenches to check for correct operation and timing.
Conclusion
These memory module designs and testbenches provide a foundation for understanding and implementing memory operations in Verilog. The testbenches ensure functionality and correctness of the modules, making them suitable for educational and practical applications in digital design.