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Auto generate dts with diplomacy (OpenXiangShan#817)
* Update mill and rocket-chip * [WIP] auto generate dts by diplomacy
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,73 @@ | ||
| // See LICENSE.SiFive for license details. | ||
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| package xiangshan | ||
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| import freechips.rocketchip.diplomacy._ | ||
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| trait HasXSDts { | ||
| this: XSCore => | ||
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| val device: SimpleDevice = new SimpleDevice("cpu", Seq("ICT,xiangshan", "riscv")) { | ||
| override def parent: Some[Device] = Some(ResourceAnchors.cpus) | ||
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| def cpuProperties: PropertyMap = Map( | ||
| "device_type" -> "cpu".asProperty, | ||
| "status" -> "okay".asProperty, | ||
| "clock-frequency" -> 0.asProperty, | ||
| "riscv,isa" -> "rv64imafdc".asProperty, | ||
| "timebase-frequency" -> 1000000.asProperty | ||
| ) | ||
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| def tileProperties: PropertyMap = { | ||
| val dcache = Map( | ||
| "d-cache-block-size" -> dcacheParameters.blockBytes.asProperty, | ||
| "d-cache-sets" -> dcacheParameters.nSets.asProperty, | ||
| "d-cache-size" -> (dcacheParameters.nSets * dcacheParameters.nWays * dcacheParameters.blockBytes).asProperty | ||
| ) | ||
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| val icache = Map( | ||
| "i-cache-block-size" -> icacheParameters.blockBytes.asProperty, | ||
| "i-cache-sets" -> icacheParameters.nSets.asProperty, | ||
| "i-cache-size" -> (icacheParameters.nSets * icacheParameters.nWays * icacheParameters.blockBytes).asProperty | ||
| ) | ||
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| val dtlb = Map( | ||
| "d-tlb-size" -> TlbEntrySize.asProperty, | ||
| "d-tlb-sets" -> 1.asProperty | ||
| ) | ||
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| val itlb = Map( | ||
| "i-tlb-size" -> TlbEntrySize.asProperty, | ||
| "i-tlb-sets" -> 1.asProperty | ||
| ) | ||
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| val mmu = Map( | ||
| "tlb-split" -> Nil, | ||
| "mmu-type" -> s"riscv,sv$VAddrBits".asProperty | ||
| ) | ||
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| val pmp = Nil | ||
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| dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ pmp | ||
| } | ||
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| def nextLevelCacheProperty: PropertyOption = { | ||
| println(memBlock) | ||
| val outer = memBlock.dcache.clientNode.edges.out.flatMap(_.manager.managers) | ||
| .filter(_.supportsAcquireB) | ||
| .flatMap(_.resources.headOption) | ||
| .map(_.owner.label) | ||
| .distinct | ||
| if (outer.isEmpty) None | ||
| else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList) | ||
| } | ||
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| override def describe(resources: ResourceBindings): Description = { | ||
| val Description(name, mapping) = super.describe(resources) | ||
| Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties) | ||
| } | ||
| } | ||
| ResourceBinding { | ||
| Resource(device, "reg").bind(ResourceAddress(hardId)) | ||
| } | ||
| } |