Rename xc.sbox.4 => xc.lut

- See #65, #52

 On branch dev/sbox-instr
 Changes to be committed:
	modified:   docs/ise-opcodes.txt
	modified:   external/riscv-binutils-gdb-2.30.patch
	modified:   rtl/coprocessor/scarv_cop_common.vh
	modified:   rtl/coprocessor/scarv_cop_idecode.v
	modified:   rtl/coprocessor/scarv_cop_palu.v
	renamed:    verif/formal/fml_chk_instr_sbox_4.v -> verif/formal/fml_chk_instr_lut.v

docs/ise-opcodes.txt

@@ -44,7 +44,7 @@ xc.mequ         31..28=0b0000             14..12=0b111 6..0=0b0101011 rd     rs1
 xc.mlte         31..28=0b0001             14..12=0b111 6..0=0b0101011 rd     rs1  crs2  crs3
 xc.mgte         31..28=0b0010             14..12=0b111 6..0=0b0101011 rd     rs1  crs2  crs3
 
-xc.sbox.4       31..28=0b1000 11=0 19=0   14..12=0b111 6..0=0b0101011 crd   crs1  crs2  crs3
+xc.lut         31..28=0b1000 11=0 19=0   14..12=0b111 6..0=0b0101011 crd   crs1  crs2  crs3
 
 #         b          op               mo              f3            opcode
 xc.madd.3   19=0 31..28=0b0011          11..10=0b00 14..12=0b111 6..0=0b0101011 crdm crs1 crs2  crs3

external/riscv-binutils-gdb-2.30.patch

@@ -472,8 +472,8 @@ index f966fb6a50..e3a89a2a02 100644
 +#define MASK_MLTE  0xf000707f
 +#define MATCH_MGTE 0x2000702b
 +#define MASK_MGTE  0xf000707f
-+#define MATCH_SBOX_4 0x8000702b
-+#define MASK_SBOX_4  0xf008787f
++#define MATCH_LUT    0x8000702b
++#define MASK_LUT     0xf008787f
 +#define MATCH_MADD_3 0x3000702b
 +#define MASK_MADD_3  0xf0087c7f
 +#define MATCH_MADD_2 0x4000702b
@@ -820,7 +820,7 @@ index 79e7214835..762230c0ea 100644
 +{"xc.mequ",     "x", "d,s,Xt,XS",          MATCH_MEQU, MASK_MEQU, match_opcode, 0},
 +{"xc.mlte",     "x", "d,s,Xt,XS",          MATCH_MLTE, MASK_MLTE, match_opcode, 0},
 +{"xc.mgte",     "x", "d,s,Xt,XS",          MATCH_MGTE, MASK_MGTE, match_opcode, 0},
-+{"xc.sbox.4",  "x", "XD,Xs,Xt,XS",         MATCH_SBOX_4, MASK_SBOX_4, match_opcode, 0},
++{"xc.lut",     "x", "XD,Xs,Xt,XS",         MATCH_LUT   , MASK_LUT   , match_opcode, 0},
 +{"xc.madd.3",    "x", "(XM),Xs,Xt,XS",        MATCH_MADD_3, MASK_MADD_3, match_opcode, 0},
 +{"xc.madd.2",    "x", "(XM),Xs,Xt",           MATCH_MADD_2, MASK_MADD_2, match_opcode, 0},
 +{"xc.msub.3",    "x", "(XM),Xs,Xt,XS",        MATCH_MSUB_3, MASK_MSUB_3, match_opcode, 0},

rtl/coprocessor/scarv_cop_common.vh

@@ -57,7 +57,7 @@ localparam SCARV_COP_SCLASS_INS       = 5'd3;
 localparam SCARV_COP_SCLASS_EXT       = 5'd4;
 localparam SCARV_COP_SCLASS_LD_LIU    = 5'd5;
 localparam SCARV_COP_SCLASS_LD_HIU    = 5'd6;
-localparam SCARV_COP_SCLASS_SBOX_4    = 5'd7;
+localparam SCARV_COP_SCLASS_LUT       = 5'd7;
 
 localparam SCARV_COP_SCLASS_PADD      = 5'b00001;
 localparam SCARV_COP_SCLASS_PSUB      = 5'b00010;

rtl/coprocessor/scarv_cop_idecode.v

@@ -116,7 +116,7 @@ wire class_mp           =
 
 wire class_bitwise      = 
     dec_mix_l || dec_mix_h  || dec_bop    || dec_ins    || 
-    dec_ext   || dec_ld_liu || dec_ld_hiu || dec_sbox_4  ;
+    dec_ext   || dec_ld_liu || dec_ld_hiu || dec_lut  ;
 
 wire class_aes          =
     dec_aessub_enc || dec_aessub_encrot || dec_aessub_dec || 
@@ -172,7 +172,7 @@ wire [4:0] subclass_bitwise =
     {5{dec_ext }} & {SCARV_COP_SCLASS_EXT } |
     {5{dec_ld_liu }} & {SCARV_COP_SCLASS_LD_LIU } |
     {5{dec_ld_hiu }} & {SCARV_COP_SCLASS_LD_HIU } |
-    {5{dec_sbox_4}} & {SCARV_COP_SCLASS_SBOX_4} ;
+    {5{dec_lut}} & {SCARV_COP_SCLASS_LUT} ;
 
 wire [4:0] subclass_aes = 
     {5{dec_aessub_enc   }} & SCARV_COP_SCLASS_AESSUB_ENC    |

rtl/coprocessor/scarv_cop_palu.v

@@ -106,7 +106,7 @@ wire bw_ins  = is_bitwise_insn && id_subclass == SCARV_COP_SCLASS_INS ;
 wire bw_ext  = is_bitwise_insn && id_subclass == SCARV_COP_SCLASS_EXT ;
 wire bw_ld_liu = is_bitwise_insn && id_subclass == SCARV_COP_SCLASS_LD_LIU;
 wire bw_ld_hiu = is_bitwise_insn && id_subclass == SCARV_COP_SCLASS_LD_HIU;
-wire bw_sbox_4 = is_bitwise_insn && id_subclass == SCARV_COP_SCLASS_SBOX_4;
+wire bw_lut   = is_bitwise_insn && id_subclass == SCARV_COP_SCLASS_LUT;
 
 // Result computation for the BOP.cr instruction
 wire [31:0] bop_result;
@@ -137,17 +137,17 @@ wire [31:0] mix_t0   =
 wire [31:0] mix_result =
     (palu_rs2 & mix_t0) | (~palu_rs2 & palu_rs3);
 
-// Result computation for the SBOX instruction.
+// Result computation for the LUT instruction.
 
-wire [63:0] sbox_concat = {64{bw_sbox_4}} & {palu_rs3, palu_rs2};
-wire [ 3:0] sbox_lut [15:0];
-wire [31:0] sbox_result;
+wire [63:0] lut_concat = {64{bw_lut}} & {palu_rs3, palu_rs2};
+wire [ 3:0] lut_lut [15:0];
+wire [31:0] lut_result;
 genvar s;
 generate for(s = 0; s < 16; s = s+ 1) begin
     if(s < 8) begin
-        assign sbox_result[4*s+3:4*s] = sbox_lut[palu_rs1[4*s+3 : 4*s]];
+        assign lut_result[4*s+3:4*s] = lut_lut[palu_rs1[4*s+3 : 4*s]];
     end
-    assign sbox_lut[s] = sbox_concat[4*s+3: 4*s];
+    assign lut_lut[s] = lut_concat[4*s+3: 4*s];
 end endgenerate
 
 // AND/ORing the various bitwise results together.
@@ -160,7 +160,7 @@ wire [31:0] result_bitwise =
     {32{bw_ins }} & {ins_result                       } |
     {32{bw_mix_l}} & {mix_result                       } |
     {32{bw_mix_h}} & {mix_result                       } |
-    {32{bw_sbox_4}} & {sbox_result                     } ;
+    {32{bw_lut}} & {lut_result                     } ;
 
 // ----------------------------------------------------------------------
 

verif/formal/fml_chk_instr_sbox_4.v → verif/formal/fml_chk_instr_lut.v

@@ -11,34 +11,34 @@
 
 `include "fml_pack_widths.vh"
 
-`VTX_CHECKER_MODULE_BEGIN(instr_sbox_4)
+`VTX_CHECKER_MODULE_BEGIN(instr_lut)
 
-wire [63:0] sbox_flat = {`CRS3, `CRS2};
-wire [3:0]  sbox[15:0];
-wire [31:0] sbox_4_result;
+wire [63:0] lut_flat = {`CRS3, `CRS2};
+wire [3:0]  lut[15:0];
+wire [31:0] lut_result;
 
 genvar i;
 generate for(i = 0; i < 16; i = i + 1) begin
 
-    assign sbox[i] = sbox_flat[(4*i)+3:4*i];
+    assign lut[i] = lut_flat[(4*i)+3:4*i];
 
     if(i < 8) begin
-        assign sbox_4_result[(4*i)+3:4*i] = sbox[`CRS1[(4*i)+3:4*i]];
+        assign lut_result[(4*i)+3:4*i] = lut[`CRS1[(4*i)+3:4*i]];
     end
 
 end endgenerate
 
 //
-// sbox_4
+// lut
 //
-`VTX_CHECK_INSTR_BEGIN(sbox_4) 
+`VTX_CHECK_INSTR_BEGIN(lut) 
 
     // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro.
-    `VTX_ASSERT_CRD_VALUE_IS(sbox_4_result)
+    `VTX_ASSERT_CRD_VALUE_IS(lut_result)
 
     // Never causes writeback to GPRS
     `VTX_ASSERT_WEN_IS_CLEAR
 
-`VTX_CHECK_INSTR_END(sbox_4)
+`VTX_CHECK_INSTR_END(lut)
 
 `VTX_CHECKER_MODULE_END