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Showing results

Public repository for PicoEVB (Xilinx Artix XC7A50T based)

C 253 65 Updated Jan 25, 2022

建议大家star此仓库,仓库会持续更新。由于部分淘宝卖家“借鉴”实验室出品的nanoDAP详情描述和资料,请大家认准实验室官方链接

C 1,183 282 Updated Apr 12, 2024

Linsn RV901T HUB75 LED "Receiver Card" Reverse Engineering

Python 573 106 Updated Apr 14, 2024

A camera ISP (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.

Python 187 46 Updated Sep 4, 2024

A Python native, OS native GUI toolkit.

Python 4,473 689 Updated Jan 21, 2025

Maia SDR is an open-source FPGA-based SDR project focusing on the ADALM Pluto

Rust 236 27 Updated Dec 1, 2024

The project ported the ThreadX RTOS to the RISC-V64 architecture, running Milk-V Duo (based on cv180x).

C 5 2 Updated Sep 10, 2024

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Verilog 391 197 Updated Jan 29, 2023

🌊 Digital timing diagram rendering engine

JavaScript 3,044 373 Updated Apr 2, 2024

A GTK+ based oscilloscope application for interfacing with various IIO devices

C 272 147 Updated Jan 17, 2025

FTDI EEPROM dumps for common JTAG FPGA programmers

74 32 Updated Nov 18, 2023

Zephyr OS running on Milk-V Duo secondary processor

C 22 5 Updated Aug 13, 2024

Must-have verilog systemverilog modules

Verilog 1,693 385 Updated Nov 7, 2024

An ultra-fast gzip file tools

C 27 Updated Apr 25, 2024

a repository trying to make ant miner t9 runs openwrt

5 1 Updated Aug 4, 2023

Register-based and RAM-based FIFOs designed in Verilog/System Verilog.

SystemVerilog 15 7 Updated Aug 11, 2024

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

SystemVerilog 370 75 Updated Sep 14, 2023

NBLI is a fast, better lossless image compression algorithm. The optimized version (fNBLI) can get 1.5x compression ratio, 8x faster encoding, and 1.2x faster decoding compared to PNG. It can also …

C++ 69 13 Updated Oct 25, 2024

一个针对 PNG 图像文件的有损压缩器,使用 Kmeans 把色彩空间量化压缩到256以下,从而利用 PNG 格式的调色板模式 (Palette) 来缩小文件大小。效果好于 https://tinypng.com

Python 74 5 Updated Sep 14, 2023

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。

Bluespec 546 44 Updated Sep 15, 2023

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

Batchfile 514 99 Updated Sep 14, 2023

An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

Verilog 272 84 Updated May 21, 2024

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器,可实现高压缩率的无损/近无损图像压缩。

Verilog 229 45 Updated Sep 18, 2024

An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII,用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。

Verilog 81 17 Updated Sep 14, 2023

An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图像解码器,可以从PNG文件中解码出原始像素。

Verilog 89 18 Updated Sep 14, 2023

An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。

Verilog 118 23 Updated Jan 26, 2024

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调试器。

Verilog 134 27 Updated Sep 14, 2023

An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据,输出标准的GZIP格式,即常见的 .gz / .tar.gz 文件的格式。

Verilog 104 23 Updated Sep 15, 2023

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。

Verilog 273 66 Updated Sep 14, 2023

An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器,用于通用数据压缩。

Verilog 78 11 Updated Sep 14, 2023
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