- 👋 Hi, I’m @seali-rgb
- 👀 I’m interested in FPGA/digital design/embedded systems.
- 🌱 I’m currently an fpga isp engineer
- 💞️ I’m looking to collaborate on networking/image processing
- 📫 How to reach me: [email protected]
Popular repositories Loading
-
xge_mac_SV_UVM_tb
xge_mac_SV_UVM_tb PublicForked from weicolor0502/xge_mac_SV_UVM_tb
SystemVerilog 1
-
verilog-ethernet
verilog-ethernet PublicForked from alexforencich/verilog-ethernet
Verilog Ethernet components for FPGA implementation
Verilog 1
-
core_ddr3_controller
core_ddr3_controller PublicForked from ultraembedded/core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
Verilog 1
-
-
-
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.