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chipsalliance/chisel
chipsalliance/chisel PublicChisel: A Modern Hardware Design Language
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chipsalliance/chisel-nix
chipsalliance/chisel-nix PublicNix template for the chisel-based industrial designing flows.
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chipsalliance/chisel-interface
chipsalliance/chisel-interface PublicThe 'missing header' for Chisel
1,657 contributions in the last year
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Activity overview
Contributed to
chipsalliance/t1,
chipsalliance/chisel-interface,
chipsalliance/chisel
and 37 other
repositories
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Contribution activity
February 2025
Created 7 commits in 3 repositories
Opened 2 pull requests in 2 repositories
chipsalliance/rvdecoderdb
1
merged
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[mill] Fix mill for bump
This contribution was made on Feb 6
sequencer/zaozi
1
open
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Vec API
This contribution was made on Feb 2
Reviewed 7 pull requests in 3 repositories
sequencer/zaozi
3 pull requests
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add zaozi jmh benchmark framework
This contribution was made on Feb 12
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Add SMT Dialect to CIRCT for SMT eDSL.
This contribution was made on Feb 12
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Fix includes dumping and update includes
This contribution was made on Feb 12
chipsalliance/chisel
3 pull requests
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Fix misoverrided publish version
This contribution was made on Feb 9
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Add publish flow for panama modules
This contribution was made on Feb 7
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Add publish flow for panama modules
This contribution was made on Feb 6
chipsalliance/t1
1 pull request
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[nix] bump mill to 0.12.5
This contribution was made on Feb 7
Created an issue in scala/scala3 that received 2 comments
static varargs cannot be observed by macro
Compiler version 3.6.2 Minimized code sum(1, 2, 3) inline def sum(args: Int*): Int = ${ sumExpr('args) } // macro need to be compile in another file …
2
comments