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  • Wuhan, China

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@freechipsproject @cnrv @chipsalliance

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  1. chipsalliance/chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.1k 615

  2. zaozi Public

    The experimental work to rewrite Chisel in pure Scala 3 and the Panama Project

    Scala 24 4

  3. chipsalliance/t1 Public

    Scala 250 30

  4. chipsalliance/rocket-chip Public

    Rocket Chip Generator

    Scala 3.3k 1.1k

  5. chipsalliance/chisel-nix Public

    Nix template for the chisel-based industrial designing flows.

    Nix 35 3

  6. chipsalliance/chisel-interface Public

    The 'missing header' for Chisel

    Scala 18 1

1,657 contributions in the last year

Contribution Graph
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Activity overview

Contributed to chipsalliance/t1, chipsalliance/chisel-interface, chipsalliance/chisel and 37 other repositories
Loading A graph representing sequencer's contributions from February 11, 2024 to February 15, 2025. The contributions are 61% commits, 29% code review, 8% pull requests, 2% issues.

Contribution activity

February 2025

Opened 2 pull requests in 2 repositories
chipsalliance/rvdecoderdb 1 merged
sequencer/zaozi 1 open
  • Vec API
    This contribution was made on Feb 2
Reviewed 7 pull requests in 3 repositories
sequencer/zaozi 3 pull requests
chipsalliance/chisel 3 pull requests
chipsalliance/t1 1 pull request

Created an issue in scala/scala3 that received 2 comments

static varargs cannot be observed by macro

Compiler version 3.6.2 Minimized code sum(1, 2, 3) inline def sum(args: Int*): Int = ${ sumExpr('args) } // macro need to be compile in another file

2 comments
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