Skip to content
View sgherbst's full-sized avatar

Block or report sgherbst

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

List of awesome semiconductor startups

Python 522 81 Updated Jan 11, 2025

Demo SoC for SiliconCompiler.

SystemVerilog 56 8 Updated Jan 21, 2025

Library of open source Process Design Kits (PDKs)

SourcePawn 32 4 Updated Jan 27, 2025

Verilator open-source SystemVerilog simulator and lint system

C++ 2,684 631 Updated Jan 26, 2025

Hardware abstraction library

Verilog 23 1 Updated Jan 27, 2025

A SystemVerilog source file pickler.

Rust 54 5 Updated Oct 20, 2024

A configurable RTL to bitstream FPGA toolchain

Python 257 7 Updated Jan 28, 2025

Share your terminal as a web application in bind/reverse mode

Go 128 23 Updated Mar 13, 2024

Demo: how to create a custom EBRICK

SystemVerilog 16 Updated Nov 20, 2024

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 1,733 595 Updated Jan 28, 2025

SvelteKit powered static site generator - npm installable on existing projects, no dedicated repo required.

Svelte 3 Updated Nov 10, 2024

Precise and flexible generation of stimuli for neuroscience experiments.

Python 7 2 Updated Nov 11, 2024

Communication framework for RTL simulation and emulation.

Python 265 22 Updated Jan 15, 2025

Generate a website from markdown with a minimum of fuss.

Svelte 9 Updated Apr 4, 2024

EDA-centric utility for linting and analyzing Tcl code.

Python 34 2 Updated Jan 19, 2025

Universal Memory Interface (UMI)

Verilog 142 12 Updated Jan 27, 2025

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Python 1,868 533 Updated Jan 28, 2025

A bounded single-producer single-consumer wait-free and lock-free queue written in C++11

C++ 951 132 Updated Jan 4, 2024

Xv6 for RISC-V

C 7,521 2,756 Updated Sep 6, 2024

Run your GitHub Actions locally 🚀

Go 57,250 1,441 Updated Jan 27, 2025

Modular hardware build system

Python 909 89 Updated Jan 28, 2025

Verilog AXI components for FPGA implementation

Verilog 1,594 467 Updated Dec 7, 2023

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,232 769 Updated Jun 27, 2024

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Scala 901 233 Updated Jan 13, 2025

List of awesome open source hardware tools, generators, and reusable designs

Python 1,964 182 Updated Jan 20, 2025

Open source machine learning accelerators

Scala 367 30 Updated Mar 24, 2024

COLMAP - Structure-from-Motion and Multi-View Stereo

C++ 8,080 1,569 Updated Jan 26, 2025

K3D lets you create 3D plots backed by WebGL with high-level API (surfaces, isosurfaces, voxels, mesh, cloud points, vtk objects, volume renderer, colormaps, etc). The primary aim of K3D-jupyter is…

Python 964 121 Updated Jul 3, 2024

Python library for operations with VCD and other digital wave files

Python 47 6 Updated Jun 6, 2024
Next