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Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
The MiBench testsuite, extended for use in general embedded environments
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Brief SystemC getting started tutorial
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
HW Design Collateral for Caliptra RoT IP
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
The FreeBSD src tree publish-only repository. Experimenting with 'simple' pull requests....
Intel Homomorphic Encryption Acceleration Library for FPGAs, including open source implementation of FPGA kernels for accelerating NTT, INTT, Keyswitch and Dyadic Multiplication modular arithmetic …
synthesiseable ieee 754 floating point library in verilog
Instruction Set Generator initially contributed by Futurewei
A complete computer science study plan to become a software engineer.
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
RISC-V Open Source Supervisor Binary Interface
Documentation for the RISC-V Supervisor Binary Interface
Working Draft of the RISC-V J Extension Specification
Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description and software programming languages
Generator Bootcamp Material: Learn Chisel the Right Way
