silicon-data-inside
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OpenRAM
OpenRAM PublicForked from VLSIDA/OpenRAM
An open-source static random access memory (SRAM) compiler.
Python
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Multiported-RAM
Multiported-RAM PublicForked from AmeerAbdelhadi/Multiported-RAM
Modular Multi-ported SRAM-based Memory
Verilog
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ngspice
ngspice PublicForked from imr/ngspice
mirror of ngspice repo at git://git.code.sf.net/p/ngspice/ngspice ngspice-ngspice
C
Repositories
- OpenRAM Public Forked from VLSIDA/OpenRAM
An open-source static random access memory (SRAM) compiler.
silicon-data-inside/OpenRAM’s past year of commit activity - sillicon-test-vehicle Public
silicon-data-inside/sillicon-test-vehicle’s past year of commit activity - trac Public Forked from edgewall/trac
Trac is an enhanced wiki and issue tracking system for software development projects (mirror)
silicon-data-inside/trac’s past year of commit activity - netgen Public Forked from RTimothyEdwards/netgen
Netgen complete LVS tool for comparing SPICE or verilog netlists
silicon-data-inside/netgen’s past year of commit activity - ngspice Public Forked from imr/ngspice
mirror of ngspice repo at git://git.code.sf.net/p/ngspice/ngspice ngspice-ngspice
silicon-data-inside/ngspice’s past year of commit activity - Modica-SRAM Public Forked from eda-ricercatore/Modica-SRAM
Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectural trade-offs between performance (using logical effort analysis) and area usage; see the source code for the HSPICE decks and MATLAB scripts that are used during architectural trade-off evaluation, and charact…
silicon-data-inside/Modica-SRAM’s past year of commit activity
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