IC design and development should be faster，simpler and more reliable

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Educational 16-bit MIPS Processor

Embedded 32-bit RISC uProcessor with SDRAM Controller

Super scalar Processor design

Float Point Add, Multiply and Division.

A very simple RISC microprocessor

GPU Project

A simplified version of the MIPS processor built using Verilog

A MIPS32 release 1 processor.

This is Lou Sir's CPU =w=

线性方程，就是一个3x3的矩阵乘以一个1x3的向量

Basic MIPS pipeline CPU written in verilog

UHD 8 bit sampling support

Bare MCPU system for DE0-Nano

Wishbone Multi-Ports Memory Slave Module

A MIPS32 System-on-Chip for the DE0-Nano FPGA

SDR receiver on FPGA Spartan 3e500 (40MHz bandwidth, 16 bit depth)

AXI BFM verification enviroment using DPI-C

MIPS32 by Verilog, Cache+SMP sim by C

Generic FIFOs

Modified version of Richard Herveille's Simple SPI core

vga

Digital frequency synthesizer for Ulach

Customized OR1200 for subsoc

A collection of RTL Verilog example code.

PIC16C5x-compatible FPGA Processor Core (Verilog-2001)

Verilog SPI master and slave