Skip to content

Commit

Permalink
update to chisel 3.4
Browse files Browse the repository at this point in the history
  • Loading branch information
ljwljwljwljw committed Oct 28, 2020
1 parent d8bfd16 commit 106f281
Show file tree
Hide file tree
Showing 5 changed files with 7 additions and 7 deletions.
2 changes: 1 addition & 1 deletion .gitmodules
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
[submodule "rocket-chip"]
path = rocket-chip
url = https://github.com/chipsalliance/rocket-chip.git
branch = 2bdb03dbca3f77ad4c378cc1b95ab4961bc1448a
branch = d6bd3c61993637c3f10544c59e861fae8af29f39
[submodule "block-inclusivecache-sifive"]
path = block-inclusivecache-sifive
url = https://github.com/RISCVERS/block-inclusivecache-sifive.git
Expand Down
2 changes: 1 addition & 1 deletion Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -133,7 +133,7 @@ clean:

init:
git submodule update --init
# do not use a recursive init to pull some not used submodules
@# do not use a recursive init to pull some not used submodules
cd ./rocket-chip/ && git submodule update --init api-config-chipsalliance hardfloat

.PHONY: verilog emu clean help init $(REF_SO)
6 changes: 3 additions & 3 deletions build.sc
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ import scalalib._
import coursier.maven.MavenRepository

object CustomZincWorkerModule extends ZincWorkerModule {
def repositories() = Seq(
def repositories() = super.repositories ++ Seq(
MavenRepository("https://maven.aliyun.com/repository/public"),
MavenRepository("https://maven.aliyun.com/repository/apache-snapshots")
)
Expand All @@ -26,7 +26,7 @@ trait CommonModule extends ScalaModule {
}

val rocketChisel = Agg(
ivy"edu.berkeley.cs::chisel3:3.3.1"
ivy"edu.berkeley.cs::chisel3:3.4.0"
)

object `rocket-chip` extends SbtModule with CommonModule {
Expand Down Expand Up @@ -68,7 +68,7 @@ object XiangShan extends CommonModule with SbtModule {
override def forkArgs = Seq("-Xmx10G")

override def ivyDeps = super.ivyDeps() ++ Agg(
ivy"edu.berkeley.cs::chisel3:3.3.2"
ivy"edu.berkeley.cs::chisel3:3.4.0-RC3"
)

override def moduleDeps = super.moduleDeps ++ Seq(`rocket-chip`, `block-inclusivecache-sifive`)
Expand Down
2 changes: 1 addition & 1 deletion rocket-chip
Submodule rocket-chip updated 241 files
2 changes: 1 addition & 1 deletion src/main/scala/xstransforms/ShowPrintTransform.scala
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ class ShowPrintTransform extends Transform with DependencyAPIMigration {

def findSubModules(m: DefModule): Unit = {
def viewStmt(s: Statement): Statement = s match {
case DefInstance(_, name, module) =>
case DefInstance(_, name, module, _) =>
ancestors(module) = ancestors(m.name) + m.name
queue += module
s
Expand Down

0 comments on commit 106f281

Please sign in to comment.