FTB(timing): delay replacer update on read (OpenXiangShan#2227)

* FTB: postpone read replacer access

this helps with timing

* FTB: add comments about replace logic

src/main/scala/xiangshan/frontend/FTB.scala

@@ -356,13 +356,18 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
     read_way.valid := hit
     read_way.bits  := hit_way
 
-    touch_set(0) := Mux(write_way.valid, write_set, read_set)
-
-    touch_way(0).valid := write_way.valid || read_way.valid
-    touch_way(0).bits := Mux(write_way.valid, write_way.bits, read_way.bits)
+    // Read replacer access is postponed for 1 cycle
+    // this helps timing
+    touch_set(0) := Mux(write_way.valid, write_set, RegNext(read_set))
+    touch_way(0).valid := write_way.valid || RegNext(read_way.valid)
+    touch_way(0).bits := Mux(write_way.valid, write_way.bits, RegNext(read_way.bits))
 
     replacer.access(touch_set, touch_way)
 
+    // Select the update allocate way
+    // Selection logic:
+    //    1. if any entries within the same index is not valid, select it
+    //    2. if all entries is valid, use replacer
     def allocWay(valids: UInt, idx: UInt): UInt = {
       if (numWays > 1) {
         val w = Wire(UInt(log2Up(numWays).W))