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test: add example of chiseltest's unit-test and generating verilog fo…
…r xs' module (OpenXiangShan#1890) * test: add example to genenrate verilog for a small module Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop * test: add DecodeUnitTest as an example for xs' chiseltest * ctrlblock: <> usage has changed, unidirection should use := * bump huancun * makefile: mv new makefile cmd into Makefile.test
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,12 @@ | ||
| # only generate a small module: example | ||
| verilog-decode: | ||
| mill -i XiangShan.test.runMain xiangshan.DecodeMain -td build --output-file DecodeUnit.v | ||
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| # chiseltest | ||
| # autorun all the chiselTest case | ||
| test: | ||
| mill -i XiangShan.test.test | ||
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| # only run DecodeUnitTest | ||
| test-DecodeUnit: | ||
| mill -i XiangShan.test.testOnly xiangshan.DecodeUnitTest |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,56 @@ | ||
| package xiangshan | ||
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| import chisel3._ | ||
| import chisel3.stage._ | ||
| import chiseltest._ | ||
| import chiseltest.ChiselScalatestTester | ||
| import chiseltest.VerilatorBackendAnnotation | ||
| import chiseltest.simulator.{VerilatorFlags, VerilatorCFlags} | ||
| import freechips.rocketchip.util.{ElaborationArtefacts, HasRocketChipStageUtils} | ||
| import org.scalatest.flatspec.AnyFlatSpec | ||
| import org.scalatest.matchers.must.Matchers | ||
| import firrtl.stage.RunFirrtlTransformAnnotation | ||
| import xstransforms.PrintModuleName | ||
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| import firrtl.options.TargetDirAnnotation | ||
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| import top.ArgParser | ||
| import xiangshan.backend.decode.DecodeUnit | ||
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| object DecodeMain extends App with HasRocketChipStageUtils { | ||
| override def main(args: Array[String]): Unit = { | ||
| val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args) | ||
| // //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config) | ||
| // If Complex Params are needed, wrap it with a Top Module to do dirty works, | ||
| // and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params" | ||
| val defaultConfig = config.alterPartial({ | ||
| // Get XSCoreParams and pass it to the "small module" | ||
| case XSCoreParamsKey => config(XSTileKey).head.copy( | ||
| // Example of how to change params | ||
| IssQueSize = 12 | ||
| ) | ||
| }) | ||
| (new ChiselStage).execute(args, Seq( | ||
| ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig) | ||
| ))) | ||
| // // Generate files when compiling. Used by ChiselDB. | ||
| // ElaborationArtefacts.files.foreach{ case (extension, contents) => | ||
| // writeOutputFile("./build", s"DecodeUnit.${extension}", contents()) | ||
| // } | ||
| } | ||
| } | ||
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| class DecodeUnitTest extends XSTester { | ||
| behavior of "DecodeUnit" | ||
| it should "pass" in { | ||
| test(new DecodeUnit()(config)).withAnnotations(Seq( | ||
| VerilatorBackendAnnotation, | ||
| VerilatorFlags(Seq()), | ||
| WriteVcdAnnotation, | ||
| TargetDirAnnotation("./build"), | ||
| RunFirrtlTransformAnnotation(new PrintModuleName) | ||
| )){ dut => | ||
| dut.clock.step(10) | ||
| } | ||
| } | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,37 @@ | ||
| package xiangshan | ||
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| import chisel3._ | ||
| import chipsalliance.rocketchip.config.Config | ||
| import chiseltest._ | ||
| import chiseltest.{VerilatorBackendAnnotation, WriteVcdAnnotation} | ||
| import chiseltest.simulator.{VerilatorCFlags, VerilatorFlags} | ||
| import firrtl.AnnotationSeq | ||
| import firrtl.stage.RunFirrtlTransformAnnotation | ||
| import org.scalatest.flatspec._ | ||
| import org.scalatest.matchers.should._ | ||
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| import top.{ArgParser, DefaultConfig} | ||
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| abstract class XSTester extends AnyFlatSpec with ChiselScalatestTester with Matchers with HasTestAnnos { | ||
| behavior of "XiangShan Module" | ||
| val defaultConfig = (new DefaultConfig) | ||
| implicit val config = defaultConfig.alterPartial({ | ||
| // Get XSCoreParams and pass it to the "small module" | ||
| case XSCoreParamsKey => defaultConfig(XSTileKey).head.copy( | ||
| // Example of how to change params | ||
| IssQueSize = 12 | ||
| ) | ||
| }) | ||
| } | ||
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| trait HasTestAnnos { | ||
| var testAnnos: AnnotationSeq = Seq() | ||
| } | ||
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| trait DumpVCD { this: HasTestAnnos => | ||
| testAnnos = testAnnos :+ WriteVcdAnnotation | ||
| } | ||
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| trait UseVerilatorBackend { this: HasTestAnnos => | ||
| testAnnos = testAnnos ++ Seq(VerilatorBackendAnnotation) | ||
| } |