Move one buffer in L1I - L2 path from L2Top to MemBlock (OpenXiangSha…

…n#2505)
sjxcn · Nov 27, 2023 · 63cac80 · 63cac80
1 parent 06999a3
commit 63cac80
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Showing 3 changed files with 16 additions and 4 deletions.
diff --git a/src/main/scala/xiangshan/L2Top.scala b/src/main/scala/xiangshan/L2Top.scala
@@ -80,7 +80,6 @@ class L2Top()(implicit p: Parameters) extends LazyModule
   val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog)
   val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog)
   val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog)
-  val l1i_to_l2_buffer = LazyModule(new TLBuffer)
   val ptw_to_l2_buffer = LazyModule(new TLBuffer)
   val i_mmio_buffer = LazyModule(new TLBuffer)
 

diff --git a/src/main/scala/xiangshan/XSTile.scala b/src/main/scala/xiangshan/XSTile.scala
@@ -56,7 +56,7 @@ class XSTile()(implicit p: Parameters) extends LazyModule
       core.memBlock.l1d_to_l2_buffer.node := core.memBlock.dcache.clientNode
   }
 
-  l2top.misc_l2_pmu := l2top.l1i_logger := l2top.l1i_to_l2_buffer.node := core.memBlock.frontendBridge.icache_node
+  l2top.misc_l2_pmu := l2top.l1i_logger := core.memBlock.frontendBridge.icache_node
   if (!coreParams.softPTW) {
     l2top.misc_l2_pmu := l2top.ptw_logger := l2top.ptw_to_l2_buffer.node := core.memBlock.ptw_to_l2_buffer.node
   }

diff --git a/src/main/scala/xiangshan/backend/MemBlock.scala b/src/main/scala/xiangshan/backend/MemBlock.scala
@@ -107,7 +107,7 @@ class fetch_to_mem(implicit p: Parameters) extends XSBundle{
 }
 
 // triple buffer applied in i-mmio path (two at MemBlock, one at L2Top)
-class InstrUncacheBuffer()(implicit p: Parameters) extends LazyModule with HasInstrMMIOConst{
+class InstrUncacheBuffer()(implicit p: Parameters) extends LazyModule with HasInstrMMIOConst {
   val node = new TLBufferNode(BufferParams.default, BufferParams.default, BufferParams.default, BufferParams.default, BufferParams.default)
   lazy val module = new InstrUncacheBufferImpl
 
@@ -127,9 +127,22 @@ class InstrUncacheBuffer()(implicit p: Parameters) extends LazyModule with HasIn
   }
 }
 
+// triple buffer applied in L1I$-L2 path (two at MemBlock, one at L2Top)
+class ICacheBuffer()(implicit p: Parameters) extends LazyModule {
+  val node = new TLBufferNode(BufferParams.default, BufferParams.default, BufferParams.default, BufferParams.default, BufferParams.default)
+  lazy val module = new ICacheBufferImpl
+
+  class ICacheBufferImpl extends LazyModuleImp(this) {
+    (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
+      out.a <> BufferParams.default(BufferParams.default(in.a))
+      in.d <> BufferParams.default(BufferParams.default(out.d))
+    }
+  }
+}
+
 // Frontend bus goes through MemBlock
 class FrontendBridge()(implicit p: Parameters) extends LazyModule {
-  val icache_node = LazyModule(new TLBuffer()).suggestName("icache").node// to keep IO port name
+  val icache_node = LazyModule(new ICacheBuffer()).suggestName("icache").node// to keep IO port name
   val instr_uncache_node = LazyModule(new InstrUncacheBuffer()).suggestName("instr_uncache").node
   lazy val module = new LazyModuleImp(this) {
   }