Makefile: bump chisel to v3.4.3 (OpenXiangShan#744)

Bump chisel to v3.4.3 and re-add `-X verilog` parameter for chisel runs. Our transform seems to have conflicts when `-X verilog` is not set.
sjxcn · Apr 2, 2021 · 96dd1a2 · 96dd1a2
1 parent c0bc1ee
commit 96dd1a2
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diff --git a/Makefile b/Makefile
@@ -54,7 +54,7 @@ SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v
 $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	mkdir -p $(@D)
 	date -R
-	mill XiangShan.test.runMain $(SIMTOP) -td $(@D) --full-stacktrace --output-file $(@F) --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf $(SIM_ARGS)
+	mill XiangShan.test.runMain $(SIMTOP) -X verilog -td $(@D) --full-stacktrace --output-file $(@F) --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf $(SIM_ARGS)
 	$(MEM_GEN) $(@D)/$(@F).conf --output_file $(@D)/$(@F).sram.v
 	@git log -n 1 >> .__head__
 	@git diff >> .__diff__

diff --git a/build.sc b/build.sc
@@ -29,7 +29,7 @@ trait CommonModule extends ScalaModule {
 }
 
 val chisel = Agg(
-  ivy"edu.berkeley.cs::chisel3:3.4.2"
+  ivy"edu.berkeley.cs::chisel3:3.4.3"
 )
 
 object `api-config-chipsalliance` extends CommonModule {