Bump difftest (OpenXiangShan#2579)

sjxcn · Dec 24, 2023 · fad4805 · fad4805
1 parent eca28d5
commit fad4805
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Showing 4 changed files with 17 additions and 88 deletions.
diff --git a/difftest b/difftest
diff --git a/src/main/scala/device/AXI4DummySD.scala b/src/main/scala/device/AXI4DummySD.scala
@@ -18,8 +18,8 @@ package device
 
 import org.chipsalliance.cde.config.Parameters
 import chisel3._
-import chisel3.experimental.ExtModule
 import chisel3.util._
+import difftest.common.DifftestSDCard
 import freechips.rocketchip.diplomacy.AddressSet
 import utility._
 
@@ -37,37 +37,6 @@ trait HasSDConst {
   def C_SIZE = NrBlock / MULT - 1
 }
 
-class SDHelper extends ExtModule with HasExtModuleInline {
-  val clk = IO(Input(Clock()))
-  val ren = IO(Input(Bool()))
-  val data = IO(Output(UInt(32.W)))
-  val setAddr = IO(Input(Bool()))
-  val addr = IO(Input(UInt(32.W)))
-
-  setInline("SDHelper.v",
-    s"""
-       |import "DPI-C" function void sd_setaddr(input int addr);
-       |import "DPI-C" function void sd_read(output int data);
-       |
-       |module SDHelper (
-       |  input clk,
-       |  input setAddr,
-       |  input [31:0] addr,
-       |  input ren,
-       |  output reg [31:0] data
-       |);
-       |
-       |  always @(negedge clk) begin
-       |    if (ren) sd_read(data);
-       |  end
-       |  always@(posedge clk) begin
-       |    if (setAddr) sd_setaddr(addr);
-       |  end
-       |
-       |endmodule
-     """.stripMargin)
-}
-
 class AXI4DummySD
 (
   address: Seq[AddressSet]
@@ -120,8 +89,7 @@ class AXI4DummySD
       wdata
     }
 
-    val sdHelper = Module(new SDHelper)
-    sdHelper.clk := clock
+    val sdHelper = DifftestSDCard()
     sdHelper.ren := (getOffset(raddr) === 0x40.U && in.ar.fire)
     sdHelper.setAddr := setAddr
     sdHelper.addr := regs(sdarg)

diff --git a/src/main/scala/device/AXI4Flash.scala b/src/main/scala/device/AXI4Flash.scala
@@ -18,41 +18,9 @@ package device
 
 import chisel3._
 import chisel3.util._
+import difftest.common.DifftestFlash
 import org.chipsalliance.cde.config.Parameters
-import chisel3.experimental.ExtModule
 import freechips.rocketchip.diplomacy.AddressSet
-import utils._
-import utility._
-
-class FlashHelper extends ExtModule with HasExtModuleInline {
-  val clk = IO(Input(Clock()))
-  val ren = IO(Input(Bool()))
-  val data = IO(Output(UInt(64.W)))
-  val addr = IO(Input(UInt(32.W)))
-
-  setInline("FlashHelper.v",
-    s"""
-       |import "DPI-C" function void flash_read
-       |(
-       |  input int addr,
-       |  output longint data
-       |);
-       |
-       |module FlashHelper (
-       |  input clk,
-       |  input [31:0] addr,
-       |  input ren,
-       |  output reg [63:0] data
-       |);
-       |
-       |  always @(posedge clk) begin
-       |    if (ren) flash_read(addr, data);
-       |  end
-       |
-       |endmodule
-     """.stripMargin)
-}
-
 
 class AXI4Flash
 (
@@ -64,9 +32,8 @@ class AXI4Flash
   override lazy val module = new AXI4SlaveModuleImp(this){
     def getOffset(addr: UInt) = addr(15,0)
 
-    val flash = Module(new FlashHelper)
-    flash.clk := clock
-    flash.ren := in.ar.fire
+    val flash = DifftestFlash()
+    flash.en := in.ar.fire
     flash.addr := Cat(0.U(16.W), getOffset(raddr))
 
     in.r.bits.data := flash.data

diff --git a/src/test/scala/top/SimTop.scala b/src/test/scala/top/SimTop.scala
@@ -75,28 +75,22 @@ class SimTop(implicit p: Parameters) extends Module {
   soc.io.systemjtag.part_number := 0.U(16.W)
   soc.io.systemjtag.version := 0.U(4.W)
 
-  val io = IO(new Bundle(){
-    val logCtrl = new LogCtrlIO
-    val perfInfo = new PerfInfoIO
-    val uart = new UARTIO
-  })
-
-  simMMIO.io.uart <> io.uart
-
-  val timer = if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) GTimer() else WireDefault(0.U(64.W))
-  val logEnable =
-    if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug))
-      (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end)
-    else WireDefault(false.B)
-  val clean = if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) WireDefault(io.perfInfo.clean) else WireDefault(false.B)
-  val dump = if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) WireDefault(io.perfInfo.dump) else WireDefault(false.B)
+  val difftest = DifftestModule.finish("XiangShan")
+
+  simMMIO.io.uart <> difftest.uart
+
+  val hasPerf = !debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug
+  val hasLog = !debugOpts.FPGAPlatform && debugOpts.EnableDebug
+  val hasPerfLog = hasPerf || hasLog
+  val timer = if (hasPerfLog) GTimer() else WireDefault(0.U(64.W))
+  val logEnable = if (hasPerfLog) WireDefault(difftest.logCtrl.enable(timer)) else WireDefault(false.B)
+  val clean = if (hasPerf) WireDefault(difftest.perfCtrl.clean) else WireDefault(false.B)
+  val dump = if (hasPerf) WireDefault(difftest.perfCtrl.dump) else WireDefault(false.B)
 
   dontTouch(timer)
   dontTouch(logEnable)
   dontTouch(clean)
   dontTouch(dump)
-
-  DifftestModule.finish("XiangShan")
 }
 
 object SimTop extends App {
+56 −7		.github/workflows/main.yml
+2 −0		Makefile
+30 −19		README.md
+12 −7		build.sc
+3 −0		config/config.h
+0 −243		doc/usage.md
+0 −61		src/main/scala/Batch.scala
+79 −36		src/main/scala/DPIC.scala
+77 −49		src/main/scala/Difftest.scala
+212 −0		src/main/scala/Gateway.scala
+0 −113		src/main/scala/Merge.scala
+142 −0		src/main/scala/Squash.scala
+72 −0		src/main/scala/common/Flash.scala
+60 −0		src/main/scala/common/LogPerfControl.scala
+12 −0		src/main/scala/common/Mem.scala
+74 −0		src/main/scala/common/SDCard.scala
+1 −1		src/test/csrc/common/dut.h
+49 −5		src/test/csrc/difftest/difftest.cpp
+31 −13		src/test/csrc/difftest/difftest.h
+5 −0		src/test/csrc/difftest/refproxy.h
+25 −15		src/test/csrc/vcs/vcs_main.cpp
+59 −34		src/test/csrc/verilator/emu.cpp
+1 −1		src/test/csrc/verilator/emu.h
+44 −0		src/test/vsrc/vcs/GfifoControl.v
+84 −47		src/test/vsrc/vcs/top.v
+1 −1		vcs.mk