一步一步写MIPS CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Tensors and Dynamic neural networks in Python with strong GPU acceleration

Development repository for the Triton language and compiler

Free resource for the book AI Compiler Development Guide

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Network Analysis in Python

Yosys Open SYnthesis Suite

Rocket Chip Generator

Chisel: A Modern Hardware Design Language

flex(词法分析)和bison(语法分析)的使用实例代码以及PDF版本的电子书

c compiler based on flex(lex), bison(yacc) and LLVM, supports LLVM IR and obj code generation. 基于flex，bison以及LLVM，使用c++11实现的类C语法编译器, 支持生成中间代码及可执行文件.

python实现的初级图论算法库:环检测问题,桥和割点,最小生成树,最短路径,欧拉路径,哈密尔顿路径,拓扑排序，最大流问题，匹配问题(匈牙利算法)

PPT模板收集，方便使用

XLS: Accelerated HW Synthesis

C++ to SuperAST translator

A collection of code samples showing usage of clang and llvm as a library

a minimal C++ interval tree implementation

Project moved to: https://github.com/llvm/llvm-project