Universal Memory Interface (UMI)

List of awesome open source hardware tools, generators, and reusable designs

CORE-V Family of RISC-V Cores

Learning FPGA, yosys, nextpnr, and RISC-V

LIN (Local Interconnect Network) bus protocol, a serial communication protocol for automotive applications.

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…

VeeR EH1 core

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edg…