Ensure the I-Cache is correctly handled in arm64_icache_sync_range

The cache_handle_range macro to handle the arm64 instruction and data
cache operations would return when it was complete. This causes problems
for arm64_icache_sync_range and arm64_icache_sync_range_checked as they
assume they can execute the i-cache handling instruction after it has been
called.

Fix this by making this assumption correct.

While here add missing instruction barriers and adjust the style to
match the rest of the assembly.

Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D18838

sys/arm64/arm64/cpufunc_asm.S

@@ -77,7 +77,6 @@ __FBSDID("$FreeBSD$");
 .if \ic != 0
 	isb
 .endif
-	ret
 .endm
 
 ENTRY(arm64_nullop)
@@ -112,13 +111,15 @@ END(arm64_tlb_flushID)
  */
 ENTRY(arm64_dcache_wb_range)
 	cache_handle_range	dcop = cvac
+	ret
 END(arm64_dcache_wb_range)
 
 /*
  * void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t)
  */
 ENTRY(arm64_dcache_wbinv_range)
 	cache_handle_range	dcop = civac
+	ret
 END(arm64_dcache_wbinv_range)
 
 /*
@@ -129,13 +130,15 @@ END(arm64_dcache_wbinv_range)
  */
 ENTRY(arm64_dcache_inv_range)
 	cache_handle_range	dcop = ivac
+	ret
 END(arm64_dcache_inv_range)
 
 /*
  * void arm64_idcache_wbinv_range(vm_offset_t, vm_size_t)
  */
 ENTRY(arm64_idcache_wbinv_range)
 	cache_handle_range	dcop = civac, ic = 1, icop = ivau
+	ret
 END(arm64_idcache_wbinv_range)
 
 /*
@@ -150,6 +153,8 @@ ENTRY(arm64_icache_sync_range)
 	cache_handle_range	dcop = cvau
 	ic	ialluis
 	dsb	ish
+	isb
+	ret
 END(arm64_icache_sync_range)
 
 /*
@@ -161,7 +166,8 @@ ENTRY(arm64_icache_sync_range_checked)
 	/* XXX: See comment in arm64_icache_sync_range */
 	cache_handle_range	dcop = cvau
 	ic	ialluis
-	dsb ish
+	dsb	ish
+	isb
 	SET_FAULT_HANDLER(xzr, x6)
 	mov	x0, #0
 	ret