In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V Single Cycle.

32-bit Superscalar RISC-V CPU

4 stage, in-order, secure RISC-V core based on the CV32E40P

RISC-V CPU Core (RV32IM)

RISC-V Assembler and Runtime Simulator

Spike, a RISC-V ISA Simulator

PulseRain Reindeer - RISCV RV32I[M] Soft CPU

A very simple and easy to understand RISC-V core.

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A FPGA friendly 32 bit RISC-V CPU implementation

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

An open-source microcontroller system based on RISC-V

OpenTitan: Open source silicon root of trust

Source files for SiFive's Freedom platforms

SonicBOOM: The Berkeley Out-of-Order Machine

Rocket Chip Generator

OpenXuantie - OpenC910 Core

IC design and development should be faster，simpler and more reliable

Open-source high-performance RISC-V processor

OpenXuantie - OpenE906 Core

The Ultra-Low Power RISC-V Core

RISC-V Instruction Set Manual