a template for automatically generating Vivado project scripts, which also includes simulation scripts for iverilog and vcs | 这是一个自动化生成 Vivado 项目脚本的模板，也包含了 iverilog 和 vcs 的仿真脚本

A template project for beginning new Chisel work

Generator Bootcamp Material: Learn Chisel the Right Way

Icarus Verilog

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

cocotb: Python-based chip (RTL) verification

Repository to host and maintain scale-sim-v2 code

This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

RISC-V Instruction Set Manual

A VIM-inspired filemanager for the console

Tab completion using fzf

simple terminal UI for git commands

Verilator open-source SystemVerilog simulator and lint system

🔧 .files, including ~/.macos — sensible hacker defaults for macOS

⛄ Possibly the smallest compiler ever

A small C11 compiler

IC design and development should be faster，simpler and more reliable

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

This is a verilog implementation of 4x4 systolic array multiplier

Open-source high-performance RISC-V processor

OpenXuantie - OpenE906 Core

The Ultra-Low Power RISC-V Core

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

An open-source microcontroller system based on RISC-V

OpenTitan: Open source silicon root of trust

Source files for SiFive's Freedom platforms

SonicBOOM: The Berkeley Out-of-Order Machine

Rocket Chip Generator