RISC-V Instruction Set Manual

A VIM-inspired filemanager for the console

Tab completion using fzf

simple terminal UI for git commands

Verilator open-source SystemVerilog simulator and lint system

🔧 .files, including ~/.macos — sensible hacker defaults for macOS

⛄ Possibly the smallest compiler ever

A small C11 compiler

IC design and development should be faster，simpler and more reliable

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

This is a verilog implementation of 4x4 systolic array multiplier

Open-source high-performance RISC-V processor

OpenXuantie - OpenE906 Core

The Ultra-Low Power RISC-V Core

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

An open-source microcontroller system based on RISC-V

OpenTitan: Open source silicon root of trust

Source files for SiFive's Freedom platforms

SonicBOOM: The Berkeley Out-of-Order Machine

Rocket Chip Generator

OpenXuantie - OpenC910 Core

In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V Single Cycle.

32-bit Superscalar RISC-V CPU

4 stage, in-order, secure RISC-V core based on the CV32E40P

RISC-V CPU Core (RV32IM)

RISC-V Assembler and Runtime Simulator

Spike, a RISC-V ISA Simulator

PulseRain Reindeer - RISCV RV32I[M] Soft CPU