The Zylin ZPU

ZPU Evo(lution), an enhanced ZPU microprocessor design in VHDL to embed within an FPGA including SoC functionality. Project currently uses Altera Cyclone devices.

zpu for ice40K

Simple stack based microprocessor

Stack CPU 🚧 Work In Progress 🚧

Fully Open Source FASOC generators built on top of open-source EDA tools

FPGArduino binary

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

Another tiny RISC-V implementation

The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.

Mega/Xmega soft core RTL design.

HIVE - a 32 bit, 8 thread, 4 register/stack hybrid, pipelined verilog soft processor core

ZPUino HDL implementation

description arduino board on verilog

Implementation of AVR Atmeg32 using VHDL

AVR Core

AVR HP, Hyper Pipelined AVR Core

Navré AVR clone (8-bit RISC)

OpenCores54x DSP

AVR CPU Core Implementation in Verilog HDL.

Reduced AVR Core for CPLD

Mostly AVR compatible FPGA soft-core

Small part of AVR CPU Core

VHDL implementation of an AVR processor.

ZPUino HDL implementation