Verification Components for Network Processors

Gate Level Implementation of a 64-bit, 5 stage pipelined ARM CPU in SystemVerilog

A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog

Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.

Design and simulate a simplified ARM single-cycle processor using SystemVerilog.

Implementation of the ARM microprocessor using SystemVerilog on Quartus II.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

1bit CPU using 74HC series logic IC.

A bit-serial CPU written in VHDL, with a simulator written in C.

MC14500 1bit CPU

A one bit CPU FPGA implementation of naoto64/1bit-CPU.

Ancient CPU Revelation