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Tiny Tapeout 06

Verilog 11 21 Updated Jan 30, 2025

This is the main repository for all the examples for the book Practical UVM

Verilog 178 111 Updated Oct 21, 2020

Examples with UVM

SystemVerilog 3 2 Updated Oct 4, 2024

I2C Master ASIC flow is implemented using Synopsys tools. From RTL to GDS.

Verilog 2 Updated May 24, 2024

It is responsible for receiving commands through UART receivers to do different system functions such as register file reading/writing or doingsome processing using ALU block and sending results th…

Verilog 1 1 Updated Jan 29, 2025

A project that covers efficient RTL design, low-power techniques, multi-clock management, synthesis, static timing analysis, self-checking testbench, DFT insertion, and post-layout analysis, encomp…

Verilog 2 1 Updated Jan 1, 2025

RTL to GDS Implementation of Low_Power_Configurable_Multi_Clock_Digital_System

Verilog 3 Updated Oct 10, 2023

VLSI Backend Design Flow / Physical Design Based on Cadence-tools

Verilog 2 Updated Aug 14, 2023

RTL to GDS Implementation of Low Power Configurable Multi Clock Digital System

Verilog 1 Updated Aug 18, 2024

It is responsible of receiving commands through UART receiver to do different system functions as register file reading/writing or doing some processing using ALU block and send result as well as C…

Verilog 1 Updated Sep 16, 2024

Design of a MOD5 counter using RTL to GDS2 flow.

Verilog 1 Updated Oct 17, 2021

This is the repository for RTL-2-GDS2 scripts of a counter for synopsys tools

Tcl 1 Updated Sep 4, 2024

v5.0

Verilog 1 Updated Oct 26, 2024

"Low Power Configurable Multi Clock Communication System" system executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) that received from UAR…

Verilog 2 Updated Sep 24, 2023

This Repository contains the flow of uart design from rtl to gds

Verilog 1 Updated Oct 3, 2024
Verilog 1 Updated Aug 8, 2024

Exploring RTL to GDS Flow in VLSI

Verilog 1 Updated May 8, 2024
Verilog 1 Updated Aug 18, 2024

This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been s…

Verilog 15 3 Updated Apr 29, 2024

• A synchronous design consists of a Counter, Encoder, and XOR and is carried Forward through the following steps:- RTL design, Test-bench design, Coverage analysis, Logic Synthesis, Equivalence ch…

3 Updated Dec 2, 2022

Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.

Verilog 8 Updated May 28, 2021

RTL to GDS via Cadence Tools

6 4 Updated May 17, 2022

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

Verilog 36 7 Updated Feb 22, 2024
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