This repo will serve as a scratchpad for my future VHDL/Verilog related projects. I intend to improve my skills in UVM, as well build up a personal library of hardware for future projects. This fir…

Pipelined RISC-V core made as a learning exercise in Verilog, SystemVerilog and UVM.

Embeded Linux Boot in RISCV32IMA

RISCV-DV based UVM Environment for IBEX Core

RISC-V processor co-simulation using SystemVerilog HDL and UVM.

an open source uvm verification platform for e200 (riscv)

Open-source high-performance RISC-V processor

A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

Basic RISC-V Test SoC

32-bit Superscalar RISC-V CPU

The Ultra-Low Power RISC-V Core

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单周期CPU，造福后人

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