Skip to content
View supriyakhatoniar's full-sized avatar
  • Tezpur University
  • Assam, India

Block or report supriyakhatoniar

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. avsd_PLL avsd_PLL Public

    Phase-Locked-Loop (PLL) IC design on Open Source Google-Skywater 130nm

  2. avsdpll_1v8 avsdpll_1v8 Public

    Forked from lakshmi-sathi/avsdpll_1v8

    8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room tempe…

  3. dvsdpiso_3v3 dvsdpiso_3v3 Public

    incomplete

  4. OpenLane OpenLane Public

    Forked from The-OpenROAD-Project/OpenLane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

    Verilog