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Network::id for maps/sets
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commit be70d30ae05665021254b0d7e69fb8d2f0a82890
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 17:04:49 2023 -0700

    cmp

    Signed-off-by: James Cherry <[email protected]>

commit 4d4ef96948afe3d6a00c4521aeb5bc74274f5737
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 16:08:50 2023 -0700

    rvo, const

    Signed-off-by: James Cherry <[email protected]>

commit bb584e4264af2bea867b17d07e8d38c0e9eb0025
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 15:05:00 2023 -0700

    const

    Signed-off-by: James Cherry <[email protected]>

commit a08fe558bca6b769b2728882258bd85aed990a27
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 14:57:33 2023 -0700

    LibertyPortPair no ptrs

    Signed-off-by: James Cherry <[email protected]>

commit 4d3bd60c109d1ce9d0589d746f4968fa7bebd90d
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 14:13:07 2023 -0700

    cleanup

    Signed-off-by: James Cherry <[email protected]>

commit dc25ff77771cfbe26f9318bad2b3c45879614783
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 14:06:13 2023 -0700

    const

    Signed-off-by: James Cherry <[email protected]>

commit 06e81586ce11a0cc06948ed78fef99353077d69e
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 14:01:10 2023 -0700

    sortByName

    Signed-off-by: James Cherry <[email protected]>

commit 9d8592aff5b246f83e47e1b94490e3cef8d8e119
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 11:57:17 2023 -0700

    sort pred

    Signed-off-by: James Cherry <[email protected]>

commit 462a8e14df8b561ddfc842addc62c4b8435b6347
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 11:09:57 2023 -0700

    const

    Signed-off-by: James Cherry <[email protected]>

commit 69f71505b684e88b22d395510429497e87bf1015
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 10:45:14 2023 -0700

    flush ConstPortSeq

    Signed-off-by: James Cherry <[email protected]>

commit 6429d578b78eac3fe7e99fcd67a120789932b2eb
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 09:19:15 2023 -0700

    rm ConstNetSet

    Signed-off-by: James Cherry <[email protected]>

commit f247930b16e40560b957a36af68947249ed1ef04
Author: James Cherry <[email protected]>
Date:   Tue Jan 17 08:50:50 2023 -0700

    sortPathNames

    Signed-off-by: James Cherry <[email protected]>

commit 4ca2b0e0af7252c7bcbc65cf141d0ce40634d329
Author: James Cherry <[email protected]>
Date:   Mon Jan 16 10:14:05 2023 -0700

    const

    Signed-off-by: James Cherry <[email protected]>

commit 3d18640d2ebc4aae3098c7e7242a554fcb64fd42
Author: James Cherry <[email protected]>
Date:   Mon Jan 16 09:41:27 2023 -0700

    set_input/ouput_delay -reference_pin

    Signed-off-by: James Cherry <[email protected]>

commit d4a0854dd2102f46f96a94fb9eb8749f1593a85f
Author: James Cherry <[email protected]>
Date:   Mon Jan 16 09:13:46 2023 -0700

    PinPairSet no malloc

    Signed-off-by: James Cherry <[email protected]>

commit a6f1583fc6a856c5ecc0dcb15a1d8b1f61e30718
Author: James Cherry <[email protected]>
Date:   Mon Jan 16 08:53:33 2023 -0700

    no malloc for EdgePins

    Signed-off-by: James Cherry <[email protected]>

commit c8e4b92e8b619109d6aa3c141c720646067ccb4b
Author: James Cherry <[email protected]>
Date:   Mon Jan 16 06:31:08 2023 +0000

    leak

commit abab99e0fc3e466d914f6c1705aa08cdc204df51
Author: James Cherry <[email protected]>
Date:   Mon Jan 16 06:07:36 2023 +0000

    leaks

commit d1913b554bb6e98b89673d80d2295f552eb4ffca
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 19:48:39 2023 -0700

    LibertyCell::checkCornerCell

    Signed-off-by: James Cherry <[email protected]>

commit bcc172237d48deed647374f9592bac70bd2d5425
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 18:19:47 2023 -0700

    rvo

    Signed-off-by: James Cherry <[email protected]>

commit 8ef9800b87f5e5548055a13afc21397f28a6bcf7
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 18:07:46 2023 -0700

    sdc net id

    Signed-off-by: James Cherry <[email protected]>

commit d7235abed04ced4e2d84e91bf9968e621268567d
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 16:00:27 2023 -0700

    range iter

    Signed-off-by: James Cherry <[email protected]>

commit a22f91a3c54c644574339d1126821d9bc8045bd6
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 15:52:50 2023 -0700

    range iter

    Signed-off-by: James Cherry <[email protected]>

commit 762615ce3de91d950eeaaa4680549a45b13e0e0a
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 15:42:19 2023 -0700

    range iter

    Signed-off-by: James Cherry <[email protected]>

commit 7e0c531613d343d23f064c24873bf5a498f6f4ce
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 12:26:49 2023 -0700

    rm removeLoadCaps, removeNetLoadCaps

    Signed-off-by: James Cherry <[email protected]>

commit f2e88c6082e2d4605e9849348008bf4065401fc8
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 12:21:03 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <[email protected]>

commit b5939666188c0b94dfe957e22bbd8a92f4786125
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 11:36:16 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <[email protected]>

commit a435081bafe10260743319f53a59cbe2ed0388b7
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 08:43:37 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <[email protected]>

commit acfb247559db7b726d47f203613488df0f7add53
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 08:38:07 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <[email protected]>

commit 7541b71da92ea15085615988a1e6ea1d4d53d8d6
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 08:00:55 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <[email protected]>

commit d033210132656ea68fa834228575b9def1d02d90
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 07:52:03 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <[email protected]>

commit ca6e9ecb7821b83ab024c4fee6df8f7fc8fc2ce2
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 07:38:12 2023 -0700

    instance_pvt_maps_

    Signed-off-by: James Cherry <[email protected]>

commit 631e4209b596386f5818045d521784db5239f58d
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 07:26:42 2023 -0700

    rm GroupPathIterator

    Signed-off-by: James Cherry <[email protected]>

commit 059c32afa87617fff530c9afa1ef8005a136739d
Author: James Cherry <[email protected]>
Date:   Sat Jan 14 20:07:44 2023 -0700

    rm ClockIterator

    Signed-off-by: James Cherry <[email protected]>

commit c65fe873a6a6696220bbb44c4ecac87d5ca978ac
Author: James Cherry <[email protected]>
Date:   Sat Jan 14 19:45:58 2023 -0700

    rvo

    Signed-off-by: James Cherry <[email protected]>

commit ce15c9a0cc78915acddc2f03749573d989ae96d6
Author: James Cherry <[email protected]>
Date:   Sun Jan 15 01:04:03 2023 +0000

    leaks

commit f97955a0c7e70b65ceb3f697ff47c0524a9b3cd4
Author: James Cherry <[email protected]>
Date:   Sat Jan 14 01:17:58 2023 +0000

    leaks

commit 7cdd65684adeb14e02827f5d93e7fab3b19af5dd
Author: James Cherry <[email protected]>
Date:   Fri Jan 13 16:07:47 2023 -0700

    leaks

    Signed-off-by: James Cherry <[email protected]>

commit ee97c7e50394a3927458e7ef09c5dbeb27719d15
Author: James Cherry <[email protected]>
Date:   Fri Jan 13 11:52:48 2023 -0700

    swig rm Tmp collections

    Signed-off-by: James Cherry <[email protected]>

commit c49935da8704e41459280971b7645fccd97e3d13
Author: James Cherry <[email protected]>
Date:   Fri Jan 13 11:18:36 2023 -0700

    swig rm Tmp types

    Signed-off-by: James Cherry <[email protected]>

commit 4320b00ce700914843006f592126cd8cc1c4657a
Author: James Cherry <[email protected]>
Date:   Fri Jan 13 10:55:10 2023 -0700

    swig rm TmpPinSet, TmpPinSeq

    Signed-off-by: James Cherry <[email protected]>

commit ff6004910980c9b09b41f63a553a4481404cc539
Author: James Cherry <[email protected]>
Date:   Fri Jan 13 10:45:06 2023 -0700

    swig rm Tmp collections

    Signed-off-by: James Cherry <[email protected]>

commit 9a5bf5c1a3e5a6d2996b3ab327fa2f3015f2ff20
Author: James Cherry <[email protected]>
Date:   Fri Jan 13 10:15:29 2023 -0700

    swig rm one TmpPinSet

    Signed-off-by: James Cherry <[email protected]>

commit f441116b56e23849485b2393b30e7086c33165a8
Author: James Cherry <[email protected]>
Date:   Fri Jan 13 09:16:56 2023 -0700

    leak

    Signed-off-by: James Cherry <[email protected]>

commit 050b08df8618340b568d9cd41fd3d5f052e2c680
Author: James Cherry <[email protected]>
Date:   Fri Jan 13 09:10:53 2023 -0700

    leak

    Signed-off-by: James Cherry <[email protected]>

commit be8c17f3a715ab53140748dc1d94698209965cf9
Author: James Cherry <[email protected]>
Date:   Fri Jan 13 08:59:06 2023 -0700

    leak

    Signed-off-by: James Cherry <[email protected]>

commit e43b82f8fb52eaeda90e3c7e76cf350ae6735ebd
Author: James Cherry <[email protected]>
Date:   Thu Jan 12 18:57:49 2023 -0700

    range iter

    Signed-off-by: James Cherry <[email protected]>

commit 8db56209de7805ac2574fd2f76170bf68afd156d
Author: James Cherry <[email protected]>
Date:   Thu Jan 12 18:08:54 2023 -0700

    GroupPathSet net id

    Signed-off-by: James Cherry <[email protected]>

commit cb7917f9827c2ea3afebd735cd4508405a0d77d4
Author: James Cherry <[email protected]>
Date:   Thu Jan 12 12:00:15 2023 -0700

    DataCheckLess net id

    Signed-off-by: James Cherry <[email protected]>

commit d9da3c62d7a76699c6ad62cebb1f5c39f89722fa
Author: James Cherry <[email protected]>
Date:   Thu Jan 12 11:42:27 2023 -0700

    rm hashPtr uses

    Signed-off-by: James Cherry <[email protected]>

commit 5bbea162bb1e023aba813598c7992c740ddf9d0b
Author: James Cherry <[email protected]>
Date:   Thu Jan 12 11:30:12 2023 -0700

    EdgePins has use net id

    Signed-off-by: James Cherry <[email protected]>

commit df38405e2ebaabdd7bbf99f3b19d78b25bd95720
Author: James Cherry <[email protected]>
Date:   Thu Jan 12 09:51:38 2023 -0700

    ExceptionPath hash use net id

    Signed-off-by: James Cherry <[email protected]>

commit 9a6dcfa54c54c9f50b14248a2449c70c20a0d977
Author: James Cherry <[email protected]>
Date:   Thu Jan 12 08:56:49 2023 -0700

    ClockInsertion, ClockLatency net id

    Signed-off-by: James Cherry <[email protected]>

commit dbb6dc0b8c93812458df31e93f08e0dbd74e8105
Author: James Cherry <[email protected]>
Date:   Thu Jan 12 08:34:03 2023 -0700

    ExceptionStateSet obj id

    Signed-off-by: James Cherry <[email protected]>

commit 70b8721c48ec0816289ee09b664c332ee095875f
Author: James Cherry <[email protected]>
Date:   Thu Jan 12 08:14:37 2023 -0700

    ClockGroups cmp

    Signed-off-by: James Cherry <[email protected]>

commit 4c6c4ca191a99cd8541e106fec3202ee14968f39
Author: James Cherry <[email protected]>
Date:   Thu Jan 12 07:38:17 2023 -0700

    ClockGroup typedef to ClockSet

    Signed-off-by: James Cherry <[email protected]>

commit 66f425315e16deee5f00b05c0a505766e7afbf01
Author: James Cherry <[email protected]>
Date:   Wed Jan 11 20:32:38 2023 -0700

    set cmps

    Signed-off-by: James Cherry <[email protected]>

commit a94866c7828af5b6714e3e4fffc13bdaf5155c0e
Author: James Cherry <[email protected]>
Date:   Wed Jan 11 19:08:09 2023 -0700

    net use id

    Signed-off-by: James Cherry <[email protected]>

commit 6348320908f42ebb5262117182e13d0024f65537
Author: James Cherry <[email protected]>
Date:   Wed Jan 11 11:52:13 2023 -0700

    exception id cmp

    Signed-off-by: James Cherry <[email protected]>

commit 0edfca41b6d6408ac17f8dfe10e697c55146c1ef
Author: James Cherry <[email protected]>
Date:   Wed Jan 11 10:47:02 2023 -0700

    range iter

    Signed-off-by: James Cherry <[email protected]>

commit 44ad77985da9f0b9e7f4780e3f233c8d94fa7db7
Author: James Cherry <[email protected]>
Date:   Wed Jan 11 08:27:58 2023 -0700

    non-ptr set cmp

    Signed-off-by: James Cherry <[email protected]>

commit 36de7d88c3fa683465604a9e16b2fc1f6bc5fdd0
Author: James Cherry <[email protected]>
Date:   Wed Jan 11 08:00:54 2023 -0700

    range iteration

    Signed-off-by: James Cherry <[email protected]>

commit 4a31a2c8d9bdae58b09af8c05a64702ea3ac6c15
Author: James Cherry <[email protected]>
Date:   Tue Jan 10 16:43:54 2023 -0700

    tcl types

    Signed-off-by: James Cherry <[email protected]>

commit 056a7447b494a4c8ecc9764650d78a5bed3d87e8
Author: James Cherry <[email protected]>
Date:   Tue Jan 10 16:10:36 2023 -0700

    tcl types

    Signed-off-by: James Cherry <[email protected]>

commit 97239554c7625ba50ee729260f08eda7dec02365
Author: James Cherry <[email protected]>
Date:   Tue Jan 10 13:10:42 2023 -0700

    use RVO

    Signed-off-by: James Cherry <[email protected]>

commit c3247d8937d483102e3e1f2b69d7ac1d331ba9d4
Author: James Cherry <[email protected]>
Date:   Mon Jan 9 22:41:20 2023 -0700

    swig template seq's

    Signed-off-by: James Cherry <[email protected]>

commit 5431c06feb256adb46858819fcf5d513cfa6b5ec
Author: James Cherry <[email protected]>
Date:   Mon Jan 9 20:50:24 2023 -0700

    swig set in template

    Signed-off-by: James Cherry <[email protected]>

commit 592ad641bf01d3beb862314a0d8986f66e258642
Author: James Cherry <[email protected]>
Date:   Mon Jan 9 17:27:25 2023 -0700

    network return containers

    Signed-off-by: James Cherry <[email protected]>

commit c95f8b77e0d6bd5ffa5ba8102413c70883c756e1
Author: James Cherry <[email protected]>
Date:   Mon Jan 9 12:15:37 2023 -0700

    PinSeq const

    Signed-off-by: James Cherry <[email protected]>

commit 702e7f9ba2f901066a38f32e67b35602b6c7bbdf
Author: James Cherry <[email protected]>
Date:   Mon Jan 9 12:02:29 2023 -0700

    InstanceSeq const

    Signed-off-by: James Cherry <[email protected]>

commit 44fc25ba4a15e4ae570d74af27c9435872a126e0
Author: James Cherry <[email protected]>
Date:   Mon Jan 9 12:01:45 2023 -0700

    NetSeq const

    Signed-off-by: James Cherry <[email protected]>

commit 03b2725c81f5d52c33c875b55056c11d482144f1
Author: James Cherry <[email protected]>
Date:   Mon Jan 9 11:33:18 2023 -0700

    rm PortPair

    Signed-off-by: James Cherry <[email protected]>

commit 3fb82a7344dc053171c9883a113764ba691ab827
Author: James Cherry <[email protected]>
Date:   Mon Jan 9 11:20:53 2023 -0700

    PinSet id

    Signed-off-by: James Cherry <[email protected]>

commit 3dd31f027e15d40d62a11d0a88ef2a115f01fb73
Author: James Cherry <[email protected]>
Date:   Sun Jan 8 15:03:33 2023 -0700

    InstanceSet id

    Signed-off-by: James Cherry <[email protected]>

commit a91dea5cc0af3bede36b3faed13adb05239ff907
Author: James Cherry <[email protected]>
Date:   Sun Jan 8 11:40:15 2023 -0700

    NetSet id

    Signed-off-by: James Cherry <[email protected]>

commit b91e4b6410134eccae7969ddcfb0b27933b2e746
Author: James Cherry <[email protected]>
Date:   Sun Jan 8 10:44:47 2023 -0700

    CellSet, PortSet id

    Signed-off-by: James Cherry <[email protected]>

commit 6f891f77fae5a6b19c1454a1a4b4e3dfae0b5c50
Author: James Cherry <[email protected]>
Date:   Sun Jan 8 10:29:25 2023 -0700

    network object sets

    Signed-off-by: James Cherry <[email protected]>

commit eb8c627a57ecc6e7c5846a01d62b090ff91c08bf
Author: James Cherry <[email protected]>
Date:   Sun Jan 8 10:09:00 2023 -0700

    PinSet1

    Signed-off-by: James Cherry <[email protected]>

commit 8e864ecbdf87000fbb3c3097c39f06173c941e35
Author: James Cherry <[email protected]>
Date:   Sat Jan 7 17:13:03 2023 -0700

    concrete network object id

    Signed-off-by: James Cherry <[email protected]>

Signed-off-by: James Cherry <[email protected]>
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jjcherry56 committed Jan 19, 2023
1 parent 440247d commit 3f7df84
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Showing 144 changed files with 4,482 additions and 4,705 deletions.
2 changes: 1 addition & 1 deletion CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ if(CMAKE_VERSION VERSION_GREATER_EQUAL 3.14)
cmake_policy(SET CMP0086 NEW)
endif()

project(STA VERSION 2.3.3
project(STA VERSION 2.4.0
LANGUAGES CXX
)

Expand Down
8 changes: 4 additions & 4 deletions dcalc/ArcDelayCalc.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -28,23 +28,23 @@ ArcDelayCalc::ArcDelayCalc(StaState *sta):
}

TimingModel *
ArcDelayCalc::model(TimingArc *arc,
ArcDelayCalc::model(const TimingArc *arc,
const DcalcAnalysisPt *dcalc_ap) const
{
const OperatingConditions *op_cond = dcalc_ap->operatingConditions();
TimingArc *corner_arc = arc->cornerArc(dcalc_ap->libertyIndex());
const TimingArc *corner_arc = arc->cornerArc(dcalc_ap->libertyIndex());
return corner_arc->model(op_cond);
}

GateTimingModel *
ArcDelayCalc::gateModel(TimingArc *arc,
ArcDelayCalc::gateModel(const TimingArc *arc,
const DcalcAnalysisPt *dcalc_ap) const
{
return dynamic_cast<GateTimingModel*>(model(arc, dcalc_ap));
}

CheckTimingModel *
ArcDelayCalc::checkModel(TimingArc *arc,
ArcDelayCalc::checkModel(const TimingArc *arc,
const DcalcAnalysisPt *dcalc_ap) const
{
return dynamic_cast<CheckTimingModel*>(model(arc, dcalc_ap));
Expand Down
3 changes: 1 addition & 2 deletions dcalc/Arnoldi.hh
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,6 @@
namespace sta {

struct delay_work;
class rcmodel;

class GateTableModel;
class Pin;
Expand Down Expand Up @@ -71,7 +70,7 @@ public:

struct timing_table
{
GateTableModel *table;
const GateTableModel *table;
const LibertyCell *cell;
const Pvt *pvt;
float in_slew;
Expand Down
39 changes: 21 additions & 18 deletions dcalc/ArnoldiDelayCalc.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -119,11 +119,11 @@ class ArnoldiDelayCalc : public RCDelayCalc
const DcalcAnalysisPt *dcalc_ap);
virtual ReducedParasiticType reducedParasiticType() const;
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
// Pass in load_cap or drvr_parasitic.
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
Expand All @@ -137,13 +137,13 @@ class ArnoldiDelayCalc : public RCDelayCalc
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void reportGateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *,
const Parasitic *,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
Expand All @@ -157,15 +157,18 @@ class ArnoldiDelayCalc : public RCDelayCalc

private:
void gateDelaySlew(const LibertyCell *drvr_cell,
GateTableModel *table_model,
const GateTableModel *table_model,
const Slew &in_slew,
float related_out_cap,
const Pvt *pvt,
// Return values.
ArcDelay &gate_delay,
Slew &drvr_slew);
void ar1_ceff_delay(delay_work *D,timing_table *tab, arnoldi1 *mod,
double *delays, double *slews);
void ar1_ceff_delay(delay_work *D,
timing_table *tab,
arnoldi1 *mod,
double *delays,
double *slews);
double ra_rdelay_1(timing_table *tab,
double ctot);
double ra_get_r(delay_work *D,
Expand Down Expand Up @@ -265,16 +268,16 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin,
const RiseFall *drvr_rf,
const DcalcAnalysisPt *dcalc_ap)
{
const Corner *corner = dcalc_ap->corner();
// set_load has precidence over parasitics.
if (!sdc_->drvrPinHasWireCap(drvr_pin)) {
if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) {
const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
Parasitic *parasitic_network =
parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap);
bool delete_parasitic_network = false;

const MinMax *cnst_min_max = dcalc_ap->constraintMinMax();
const OperatingConditions *op_cond = dcalc_ap->operatingConditions();
const Corner *corner = dcalc_ap->corner();
if (parasitic_network == nullptr) {
Wireload *wireload = sdc_->wireload(cnst_min_max);
if (wireload) {
Expand Down Expand Up @@ -317,7 +320,7 @@ void
ArnoldiDelayCalc::inputPortDelay(const Pin *drvr_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap)
{
RCDelayCalc::inputPortDelay(drvr_pin, in_slew, rf, parasitic, dcalc_ap);
Expand All @@ -327,7 +330,7 @@ ArnoldiDelayCalc::inputPortDelay(const Pin *drvr_pin,

int j;
if (parasitic) {
rcmodel_ = reinterpret_cast<rcmodel*>(parasitic);
rcmodel_ = reinterpret_cast<rcmodel*>(const_cast<Parasitic*>(parasitic));
pin_n_ = rcmodel_->n;
if (pin_n_ >= _pinNmax) {
_pinNmax *= 2;
Expand Down Expand Up @@ -358,10 +361,10 @@ ArnoldiDelayCalc::inputPortDelay(const Pin *drvr_pin,

void
ArnoldiDelayCalc::gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
Expand All @@ -374,7 +377,7 @@ ArnoldiDelayCalc::gateDelay(const LibertyCell *drvr_cell,
drvr_library_ = drvr_cell->libertyLibrary();
drvr_parasitic_ = drvr_parasitic;
ConcreteParasitic *drvr_cparasitic =
reinterpret_cast<ConcreteParasitic*>(drvr_parasitic);
reinterpret_cast<ConcreteParasitic*>(const_cast<Parasitic*>(drvr_parasitic));
rcmodel_ = dynamic_cast<rcmodel*>(drvr_cparasitic);
GateTimingModel *model = gateModel(arc, dcalc_ap);
GateTableModel *table_model = dynamic_cast<GateTableModel*>(model);
Expand All @@ -392,7 +395,7 @@ ArnoldiDelayCalc::gateDelay(const LibertyCell *drvr_cell,

void
ArnoldiDelayCalc::gateDelaySlew(const LibertyCell *drvr_cell,
GateTableModel *table_model,
const GateTableModel *table_model,
const Slew &in_slew,
float related_out_cap,
const Pvt *pvt,
Expand Down Expand Up @@ -454,10 +457,10 @@ ArnoldiDelayCalc::loadDelay(const Pin *load_pin,

void
ArnoldiDelayCalc::reportGateDelay(const LibertyCell *,
TimingArc *,
const TimingArc *,
const Slew &,
float,
Parasitic *,
const Parasitic *,
float,
const Pvt *,
const DcalcAnalysisPt *,
Expand Down
2 changes: 1 addition & 1 deletion dcalc/ArnoldiReduce.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -451,7 +451,7 @@ ArnoldiReduce::pinCapacitance(ParasiticNode *node)
if (lib_port)
pin_cap = sdc_->pinCapacitance(pin,rf_, op_cond_, corner_, cnst_min_max_);
else if (network_->isTopLevelPort(pin))
pin_cap = sdc_->portExtCap(port, rf_, cnst_min_max_);
pin_cap = sdc_->portExtCap(port, rf_, corner_, cnst_min_max_);
}
return pin_cap;
}
Expand Down
13 changes: 5 additions & 8 deletions dcalc/DelayCalc.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -74,16 +74,13 @@ isDelayCalcName(const char *name)
return delay_calcs->hasKey(name);
}

StringSeq *
StringSeq
delayCalcNames()
{
StringSeq *names = new StringSeq;
DelayCalcMap::Iterator dcalc_iter(delay_calcs);
while (dcalc_iter.hasNext()) {
MakeArcDelayCalc maker;
const char *name;
dcalc_iter.next(name, maker);
names->push_back(name);
StringSeq names;
for (auto name_dcalc : *delay_calcs) {
const char *name = name_dcalc.first;
names.push_back(name);
}
return names;
}
Expand Down
2 changes: 1 addition & 1 deletion dcalc/DelayCalc.i
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@

%inline %{

TmpStringSeq *
StringSeq
delay_calc_names()
{
return sta::delayCalcNames();
Expand Down
20 changes: 10 additions & 10 deletions dcalc/DmpCeff.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,7 @@ class DmpError : public Exception

static double
gateModelRd(const LibertyCell *cell,
GateTableModel *gate_model,
const GateTableModel *gate_model,
const RiseFall *rf,
double in_slew,
double c2,
Expand Down Expand Up @@ -1546,7 +1546,7 @@ void
DmpCeffDelayCalc::inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap)
{
dmp_alg_ = nullptr;
Expand All @@ -1556,10 +1556,10 @@ DmpCeffDelayCalc::inputPortDelay(const Pin *port_pin,

void
DmpCeffDelayCalc::gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
Expand Down Expand Up @@ -1606,7 +1606,7 @@ void
DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library,
const LibertyCell *drvr_cell,
const Pvt *pvt,
GateTableModel *gate_model,
const GateTableModel *gate_model,
const RiseFall *rf,
double in_slew,
float related_out_cap,
Expand Down Expand Up @@ -1647,10 +1647,10 @@ DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library,

float
DmpCeffDelayCalc::ceff(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap)
Expand All @@ -1668,10 +1668,10 @@ DmpCeffDelayCalc::ceff(const LibertyCell *drvr_cell,

void
DmpCeffDelayCalc::reportGateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
Expand Down Expand Up @@ -1715,7 +1715,7 @@ DmpCeffDelayCalc::reportGateDelay(const LibertyCell *drvr_cell,

static double
gateModelRd(const LibertyCell *cell,
GateTableModel *gate_model,
const GateTableModel *gate_model,
const RiseFall *rf,
double in_slew,
double c2,
Expand Down
16 changes: 8 additions & 8 deletions dcalc/DmpCeff.hh
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,32 +37,32 @@ public:
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
// return values
ArcDelay &gate_delay,
Slew &drvr_slew);
virtual float ceff(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap);
virtual void reportGateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
Expand All @@ -81,7 +81,7 @@ protected:
void setCeffAlgorithm(const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
GateTableModel *gate_model,
const GateTableModel *gate_model,
const RiseFall *rf,
double in_slew,
float related_out_cap,
Expand Down
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