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Fix constant ports
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@gaoyichuan
gaoyichuan committed Sep 12, 2022
1 parent d398384 commit c4cf67d
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Showing 2 changed files with 26 additions and 26 deletions.
26 changes: 13 additions & 13 deletions thinpad_top.srcs/sim_1/new/tb/lab2_tb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -49,23 +49,23 @@ module lab2_tb;

.txd(),
.rxd(1'b1),
.uart_rdn(1'b1),
.uart_wrn(1'b1),
.uart_dataready(),
.uart_tbre(),
.uart_tsre(),
.uart_rdn(),
.uart_wrn(),
.uart_dataready(1'b0),
.uart_tbre(1'b0),
.uart_tsre(1'b0),
.base_ram_data(),
.base_ram_addr(),
.base_ram_ce_n(1'b1),
.base_ram_oe_n(1'b1),
.base_ram_we_n(1'b1),
.base_ram_be_n(1'b1),
.base_ram_ce_n(),
.base_ram_oe_n(),
.base_ram_we_n(),
.base_ram_be_n(),
.ext_ram_data(),
.ext_ram_addr(),
.ext_ram_ce_n(1'b1),
.ext_ram_oe_n(1'b1),
.ext_ram_we_n(1'b1),
.ext_ram_be_n(1'b1),
.ext_ram_ce_n(),
.ext_ram_oe_n(),
.ext_ram_we_n(),
.ext_ram_be_n(),
.flash_d(),
.flash_a(),
.flash_rp_n(),
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26 changes: 13 additions & 13 deletions thinpad_top.srcs/sim_1/new/tb/lab3_tb.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -87,23 +87,23 @@ module lab3_tb;

.txd(),
.rxd(1'b1),
.uart_rdn(1'b1),
.uart_wrn(1'b1),
.uart_dataready(),
.uart_tbre(),
.uart_tsre(),
.uart_rdn(),
.uart_wrn(),
.uart_dataready(1'b0),
.uart_tbre(1'b0),
.uart_tsre(1'b0),
.base_ram_data(),
.base_ram_addr(),
.base_ram_ce_n(1'b1),
.base_ram_oe_n(1'b1),
.base_ram_we_n(1'b1),
.base_ram_be_n(1'b1),
.base_ram_ce_n(),
.base_ram_oe_n(),
.base_ram_we_n(),
.base_ram_be_n(),
.ext_ram_data(),
.ext_ram_addr(),
.ext_ram_ce_n(1'b1),
.ext_ram_oe_n(1'b1),
.ext_ram_we_n(1'b1),
.ext_ram_be_n(1'b1),
.ext_ram_ce_n(),
.ext_ram_oe_n(),
.ext_ram_we_n(),
.ext_ram_be_n(),
.flash_d(),
.flash_a(),
.flash_rp_n(),
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