[OCCAMY] Workaround for dependency between iss .so and memory .so

occamy.py

@@ -51,6 +51,10 @@ def __init__(self, parent, name, arch, binary, debug_binaries):
         # Components
         #
 
+        # Bootrom
+        rom = memory.memory.Memory(self, 'rom', size=arch.bootrom.size,
+            stim_file=self.get_file_path('pulp/chips/occamy/bootrom.bin'))
+
         # CVA6
         # TODO binary loader is bypassing this boot addr
         host = iss.Riscv(self, 'host', isa="rv64imafdc", boot_addr=0x0100_0000, timed=False,
@@ -85,10 +89,6 @@ def __init__(self, parent, name, arch, binary, debug_binaries):
         # Soc control
         soc_reg = SocReg(self, 'soc_reg')
 
-        # Bootrom
-        rom = memory.memory.Memory(self, 'rom', size=arch.bootrom.size,
-            stim_file=self.get_file_path('pulp/chips/occamy/bootrom.bin'))
-
         # Narrow SPM
         spm_narrow = memory.memory.Memory(self, 'narrow_spm', size=arch.spm_narrow.size)
 

pulp/snitch/sequencer.cpp

@@ -47,6 +47,7 @@ class OffloadReq
     iss_insn_t insn;
     bool is_write;
     unsigned int frm;
+    unsigned int fmode;
 };
 
 

pulp/snitch/snitch_core.py

@@ -22,6 +22,19 @@
 
 
 def add_latencies(isa):
+
+    # To model the fact that alt fp16 and fp18 instructions are dynamically enabled through a
+    # CSR, we insert a stub which call the proper handler depending on the CSR value
+    xf16_isa = isa.get_isa('f16')
+    for insn in xf16_isa.get_insns():
+        insn.exec_func = insn.exec_func + '_switch'
+        insn.exec_func_fast = insn.exec_func_fast + '_switch'
+
+    xf8_isa = isa.get_isa('f8')
+    for insn in xf8_isa.get_insns():
+        insn.exec_func = insn.exec_func + '_switch'
+        insn.exec_func_fast = insn.exec_func_fast + '_switch'
+
     # Set snitch instruction latency:
     # 1. the latency of instruction, the core stalls for n cycles at the current instruction. (insn->latency)
     # 2. the latency of output register, the output is ready after n cycles to check data dependency. (reg.latency)
@@ -106,6 +119,7 @@ def __init__(self,
             "cpu/iss/src/resource.cpp",
             "cpu/iss/src/trace.cpp",
             "cpu/iss/src/syscalls.cpp",
+            "cpu/iss/src/memcheck.cpp",
             "cpu/iss/src/htif.cpp",
             "cpu/iss/src/mmu.cpp",
             "cpu/iss/src/pmp.cpp",
@@ -179,7 +193,7 @@ def __init__(self,
             timed: bool=False):
 
 
-        isa_instance = cpu.iss.isa_gen.isa_riscv_gen.RiscvIsa("snitch_" + isa, isa,
+        isa_instance = cpu.iss.isa_gen.isa_riscv_gen.RiscvIsa("snitch_fp_ss_" + isa, isa,
             extensions=[ Rv32ssr(), Rv32frep(), Xdma(), Xf16(), Xf16alt(), Xf8(), Xfvec(), Xfaux() ] )
 
         add_latencies(isa_instance)
@@ -212,6 +226,7 @@ def __init__(self,
             "cpu/iss/src/resource.cpp",
             "cpu/iss/src/trace.cpp",
             "cpu/iss/src/syscalls.cpp",
+            "cpu/iss/src/memcheck.cpp",
             "cpu/iss/src/htif.cpp",
             "cpu/iss/src/mmu.cpp",
             "cpu/iss/src/pmp.cpp",