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Commits on Oct 1, 2021

• core: update parameters and module organizations (OpenXiangShan#1080)

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Commits on Sep 30, 2021

• Support multi-bank at L2 (OpenXiangShan#1083)

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• Refactor cache params (OpenXiangShan#1078)

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Commits on Sep 28, 2021

• rs: latch jump pc when deq is blocked (OpenXiangShan#1076)

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• configs, core: update some parameters (OpenXiangShan#1072)

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• misc: code clean up (OpenXiangShan#1073)

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Commits on Sep 27, 2021

• dcache: support alwaysReleaseData parameter (OpenXiangShan#1070)

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• top: fix debugIntNode on multi-core (OpenXiangShan#1071)

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• rs: add pcMem to store pc for jalr instructions (OpenXiangShan#1064)

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• 128KB L1D + non-inclusive L2/L3 (OpenXiangShan#1051)

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• misc: use Definition and Instance for modules (OpenXiangShan#1067)

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Commits on Sep 26, 2021

• Merge pull request OpenXiangShan#1057 from OpenXiangShan/ubtb-1K

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• IFU: add performance counters

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• IFU: temporarily let mmio req access fault

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Commits on Sep 25, 2021

• backend: optimize aluOpType to 7 bits (OpenXiangShan#1061)

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• Bmu: support zbk* instruction (OpenXiangShan#1059)

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Commits on Sep 23, 2021

• BPU: Modify ubtb to direct mapped from fully associative

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• Integer SRT16 Divider (OpenXiangShan#1019)

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Commits on Sep 22, 2021

• Merge branch 'master' into me-timing

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• backend, freelist: shrink verilog size by using scala variable

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• backend: add performance counters for first issue (OpenXiangShan#1050)

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• Merge pull request OpenXiangShan#1036 from OpenXiangShan/false_hit_fix

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Commits on Sep 21, 2021

• backend, freelist: simplify walk logic

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Commits on Sep 20, 2021

• rs, fma: separate fadd and fmul issue (OpenXiangShan#1042)

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Commits on Sep 19, 2021

• backend,rs: load balance for issue selection (OpenXiangShan#1048)

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• backend, freelist: remove unused log & assertions

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• backend, freelist: modify free list allocatePhyReg logic

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Commits on Sep 18, 2021

• core: add timer counters for important stages (OpenXiangShan#1045)

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• Merge branch 'master' into me-timing

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• backend, freelist: opt flush process in MEFreeList

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Commits on Sep 17, 2021

• ICache: fix physical tag bug

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• ICache: fix fencei not connected

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• modify dma bus width form 256 to 128 bits (OpenXiangShan#1041)

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• regfile: manually reset every registers (OpenXiangShan#1038)

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Commits on Sep 16, 2021

• MissQueue: fix perf bug when MissQ merges load miss (OpenXiangShan#1037)

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