fix:add uncache connect

tkj666 · Jul 18, 2022 · 9b1d7ba · 9b1d7ba
1 parent 4422a92
commit 9b1d7ba
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Showing 3 changed files with 4 additions and 1 deletion.
diff --git a/src/vsrc/axi-crossbar b/src/vsrc/axi-crossbar
diff --git a/src/vsrc/cpu_top.sv b/src/vsrc/cpu_top.sv
@@ -173,10 +173,11 @@ module cpu_top
     logic [1:0] wb_dcache_flush;  // flush dcache if excp
     logic [1:0][`RegBus] wb_dcache_flush_pc;
     logic [2:0] mem_cache_wr_type;
-    logic dcache_ack, dcache_ready;
+    logic dcache_ack, dcache_ready, mem_uncache_en;
 
     assign mem_cache_ce = mem_cache_signal[0].ce | mem_cache_signal[1].ce;
     assign mem_cache_we = mem_cache_signal[0].we | mem_cache_signal[1].we;
+    assign mem_uncache_en = mem_cache_signal[0].uncache_en | mem_cache_signal[0].uncache_en;
     assign mem_cache_sel =  mem_cache_signal[0].we ? mem_cache_signal[0].sel : mem_cache_signal[1].we ? mem_cache_signal[1].sel : 0;
     assign mem_cache_rd_type = mem_cache_signal[0].ce ? mem_cache_signal[0].rd_type : mem_cache_signal[1].ce ? mem_cache_signal[1].rd_type : 0;
     assign mem_cache_wr_type =  mem_cache_signal[0].ce ? mem_cache_signal[0].wr_type : mem_cache_signal[1].ce ? mem_cache_signal[1].wr_type : 0;

diff --git a/src/vsrc/pipeline/4_mem/mem1.sv b/src/vsrc/pipeline/4_mem/mem1.sv
@@ -154,6 +154,7 @@ module mem1
         dcache_rreq_o = 0;
         if (advance & access_mem & mem_access_valid) begin
             dcache_rreq_o.ce = 1;
+            dcache_rreq_o.uncache = uncache_en;
             dcache_rreq_o.pc = ex_i.instr_info.pc;
             case (aluop_i)
                 `EXE_LD_B_OP, `EXE_LD_BU_OP: begin