RAM-Verification-using-UVM

Build a UVM Environment for an parametrized memory module, including uvm testbench architecture components such as; sequencer, driver, monitor, scoreboard and subscriber. design was verified using QuestaSim.

• Memory Block Diagram:

• Memory Testbench Architecture:

• Project Workings:

after including the SV files in a project, and simulating the top module, the tb automatically prints out on the transcript window, whether each memory reading instance was successful or failed.