Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.

Fast, interactive Julia/GTK+ plots (+Smith charts +Gtk widget +Cairo-only images)

Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

Automatic generation of real number models from analog circuits

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

Open Source PHY v2

HSPICE and MATLAB simulation files of a tracking SAR ADC

A low noise nanovoltmeter design files and code

gnucap mirror (read only)

Raspberry Pi powered High Altitude Weather Balloon

Pure Python async code for talking to the BitScope micro

Code for "Improving Noise Tolerance of Mixed-Signal Neural Networks" https://arxiv.org/abs/1904.01705

A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

A 2 stage CMOS OTA with Differential amplifier with active load as the first stage followed by Common Source stage using Cadence

This repository contains the files (schematic, test bench, simulation results) from the course Mixed-Signal Design(undergrad)

Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process

3bit digitally controlled PWM Generator using eSim, using ngveri(Makerchip) and ngspice

Verilog-A test block for estimating noise and offset of a dynamic comparator in a transient simulation. Uses the Confidence-Boosting concept published at NEWCAS 2024.

Notes along the way...

Mixed signal PCB with op-amps, filters, ADC/DAC interfaces. ADACUS