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A Primer on Memory Consistency and Cache Coherence (Second Edition) 翻译计划

211 41 Updated May 5, 2024

EE 260 Winter 2017: Advanced VLSI Design

Verilog 60 26 Updated Dec 13, 2016

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 1,805 608 Updated Mar 7, 2025

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Python 3,070 402 Updated Oct 28, 2024

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Python 1,437 386 Updated Feb 26, 2025

A toop for openlava data-collection, data-analysis and information display.

Python 19 9 Updated Jul 17, 2024

Superconductor Circuit Simulator

JavaScript 1 Updated Jul 8, 2018

The official repository for the gem5 computer-system architecture simulator.

C++ 1,866 1,337 Updated Mar 7, 2025

My personal notes

1,659 430 Updated Feb 1, 2023

算法竞赛入门经典第2版-习题选解

C++ 567 126 Updated Sep 8, 2021

A python library for instrument control and superconducting QIP experiments.

Python 25 11 Updated Jun 6, 2017

Measurement and control software for superconducting qubits.

MATLAB 38 15 Updated Jul 9, 2021

Superconductor Circuit Simulator

C++ 83 38 Updated Feb 4, 2025

📖【译】UCB CS61a SICP Python

CSS 2,228 336 Updated Jul 14, 2023

Twisty Timer is a material design twisty puzzle timer for Android. It uses the TNoodle library to generate scramble sequences for all current official speedsolving puzzles.

Java 251 53 Updated Jul 21, 2023

LaTeX source and supporting code for Think Python, 2nd edition, by Allen Downey.

TeX 2,554 1,665 Updated Apr 9, 2024

📚 Solutions for C++ Primer 5th exercises.

C++ 3,305 1,437 Updated Jul 30, 2023