OpenTitan: Open source silicon root of trust

Application Level Fault Injection for Pytorch

RISC-V SystemC-TLM simulator

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The…

High-performance simulator of quantum circuits

MSVC's implementation of the C++ Standard Library.

aw_nas: A Modularized and Extensible NAS Framework

http://vlsiarch.eecs.harvard.edu/research/recommendation/

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

SV/UVM based open-source instruction generator for RISC-V processor verification

SiliconCompiler is an open source compiler framework that automates translation from source code to silicon.

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

a language for fast, portable data-parallel computation

Data-driven simulation for training and evaluating full-scale autonomous vehicles.

Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)

An abstraction library for interfacing EDA tools

GNU toolchain for RISC-V, including GCC

A library for researching neural networks compression and acceleration methods.

Deep Learning Examples

This is a list of interesting papers and projects about TinyML.

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.

RSD: RISC-V Out-of-Order Superscalar Processor

Python-based IP-XACT parser

ArrayFire: a general purpose GPU library.

Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration

Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)