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16 stars written in Verilog
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PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,198 765 Updated Jun 27, 2024

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,643 1,019 Updated Mar 24, 2021

IC design and development should be faster,simpler and more reliable

Verilog 1,879 573 Updated Dec 31, 2021

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 1,708 582 Updated Jan 3, 2025

Must-have verilog systemverilog modules

Verilog 1,684 386 Updated Nov 7, 2024

The Ultra-Low Power RISC-V Core

Verilog 1,351 348 Updated Oct 9, 2024

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

Verilog 165 44 Updated Oct 9, 2019

Fixed Point Math Library for Verilog

Verilog 123 35 Updated Jul 17, 2014

AXI DMA 32 / 64 bits

Verilog 102 33 Updated Jul 17, 2014

8051 core

Verilog 99 33 Updated Jul 17, 2014

AHB DMA 32 / 64 bits

Verilog 52 21 Updated Jul 17, 2014

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) h…

Verilog 39 2 Updated Dec 3, 2023

Enhanced 6502/65C02 Microprogrammed FPGA Processor Core (Verilog-2001)

Verilog 31 9 Updated Mar 15, 2022

Fully-differential asynchronous non-binary 12-bit SAR-ADC

Verilog 29 8 Updated Jun 13, 2023
Verilog 25 11 Updated Jun 12, 2022

Mini-Risc core

Verilog 6 8 Updated Dec 4, 2017