Computer Engineering student at Alma Mater Studiorum - Università di Bologna
- Modigliana, Forlì-Cesena, Italy
Pinned Loading
-
cva6_te_connector
cva6_te_connector PublicHardware module to connect a CVA6 core to a Efficient Trace specification compliant Trace Encoder
SystemVerilog
-
CGProjectThreeJS
CGProjectThreeJS PublicFinal project for "Fondamenti di Computer Graphics M - modulo 2" class
JavaScript
-
CGProject
CGProject PublicFinal project for "Fondamenti di Computer Graphics M - modulo 1" class
JavaScript
-
DLX-RISCV-simulator
DLX-RISCV-simulator PublicForked from FilippoComastri/DLX-RISCV-simulator
TypeScript 1
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.