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UC Berkeley Architecture Research

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  1. chipyard chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala 1.8k 693

  2. chiseltest chiseltest Public archive

    The batteries-included testing and formal verification library for Chisel-based RTL designs.

    Scala 231 76

  3. dsptools dsptools Public

    A Library of Chisel3 Tools for Digital Signal Processing

    Scala 234 39

  4. chisel-tutorial chisel-tutorial Public

    chisel tutorial exercises and answers

    Scala 718 198

Repositories

Showing 10 of 194 repositories
  • zephyr Public Forked from zephyrproject-rtos/zephyr

    Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

    ucb-bar/zephyr’s past year of commit activity
    C 0 Apache-2.0 7,216 0 0 Updated Apr 6, 2025
  • sp24-Baremetal-IDE Public Forked from ucb-bar/Baremetal-IDE

    A submodule of Chipyard https://github.com/ucb-bar/chipyard

    ucb-bar/sp24-Baremetal-IDE’s past year of commit activity
    HTML 1 11 0 1 Updated Apr 6, 2025
  • XNNPACK Public Forked from google/XNNPACK

    High-efficiency floating-point neural network inference operators for mobile, server, and Web

    ucb-bar/XNNPACK’s past year of commit activity
    C 0 429 0 0 Updated Apr 5, 2025
  • Baremetal-NN Public

    Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.

    ucb-bar/Baremetal-NN’s past year of commit activity
    C 29 5 1 0 Updated Apr 5, 2025
  • tacit_decoder Public
    ucb-bar/tacit_decoder’s past year of commit activity
    Rust 4 0 0 1 Updated Apr 5, 2025
  • tacit Public

    Timing Accurate Core Instruction Trace

    ucb-bar/tacit’s past year of commit activity
    Scala 0 0 0 0 Updated Apr 5, 2025
  • matlib Public Forked from wid4soe/matlib

    Matrix Library for RISC-V Accelerators

    ucb-bar/matlib’s past year of commit activity
    Python 1 BSD-3-Clause 3 0 0 Updated Apr 3, 2025
  • shuttle Public

    A Rocket-based RISC-V superscalar in-order core

    ucb-bar/shuttle’s past year of commit activity
    Scala 31 5 1 0 Updated Apr 3, 2025
  • ara-wrapper Public
    ucb-bar/ara-wrapper’s past year of commit activity
    Scala 2 0 0 0 Updated Apr 3, 2025
  • chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    ucb-bar/chipyard’s past year of commit activity
    Scala 1,805 BSD-3-Clause 693 148 (3 issues need help) 33 Updated Apr 3, 2025
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