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v-i-s-h-n-u-b/README.md

Hi there, I'm Vishnu Bharadwaj

  • 🌱 I’m currently learning RTL Design and VLSI.
  • 👯 I’m looking to collaborate on Exciting Hardware projects pertaining to my domain.
  • 🔭 I’m currently working on the following projects:
    • FPGA-Based Hardware Implementation of CNN and Activation Functions for Machine Learning Acceleration.
  • 📫 How to reach me: Please do message me on my Linkedin

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  1. AXI4-Lite AXI4-Lite Public

    SystemVerilog

  2. ASIC-Design-Roadmap ASIC-Design-Roadmap Public

    Forked from abdelazeem201/ASIC-Design-Roadmap

    The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…

    Verilog

  3. 8-bit-CPU 8-bit-CPU Public

    Simple CPU Design in Verilog with MIPS-like Architecture, featuring Branch Prediction and Interrupt Control. - Verilog

  4. Traffic-light-controller Traffic-light-controller Public

    FPGA implementation of North South, East West, Emergency Vehicle Response, Pedestrian Crossing - Verilog

  5. Logic-Synthesis-Techniques-EC801 Logic-Synthesis-Techniques-EC801 Public

    Code scripts - LST 7th sem

    Jupyter Notebook

  6. Lung_Image_Segmentation Lung_Image_Segmentation Public

    Jupyter Notebook