varshitha-raj

varshitha-raj

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8 stars written in Verilog

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Verilog 292 78 Updated Apr 30, 2024

uvm AXI BFM(bus functional model)

Verilog 236 113 Updated Jun 23, 2013

This is the main repository for all the examples for the book Practical UVM

Verilog 178 111 Updated Oct 21, 2020

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

Verilog 96 33 Updated Dec 29, 2024

my UVM training projects

Verilog 29 11 Updated Mar 14, 2019

All the projects and assignments done as part of VLSI course.

Verilog 18 4 Updated Sep 23, 2020

Verilog Programs used for advanced VLSI Design

Verilog 2 Updated Feb 28, 2022

Examples of simple modules in Verilog.

Verilog 2 Updated Aug 22, 2017