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picolibc - a C library designed for embedded 32- and 64- bit systems.
A system daemon to allow session software to update firmware
This repo is a mirror of the official userspace-rcu git found at git://git.lttng.org/userspace-rcu.git. liburcu is a LGPLv2.1 userspace RCU (read-copy-update) library. This data synchronization lib…
Mirror of Apache HTTP Server. Issues: http://issues.apache.org
Box64 - Linux Userspace x86_64 Emulator with a twist, targeted at ARM64, RV64 and LoongArch Linux devices
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
Automated upstream mirror for libbpf stand-alone build.
Verilator open-source SystemVerilog simulator and lint system
GEP (GDB Enhanced Prompt) - a GDB plug-in to enhance your GDB with fzf history search, fzf tab auto-completion, fish-like autosuggestions, and more!
ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.
A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.
MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems
PyPy is a very fast and compliant implementation of the Python language.
RISC-V microcontroller IP core developed in Verilog
Capturing SSL/TLS plaintext without a CA certificate using eBPF. Supported on Linux/Android kernels for amd64/arm64.
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Build a minimal multi-tasking OS kernel for RISC-V from scratch
Dolphin is a GameCube / Wii emulator, allowing you to play games for these two platforms on PC with improvements.
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
The Patterns of Scalable, Reliable, and Performant Large-Scale Systems
