Update set_wire_rc command (The-OpenROAD-Project#682)

waarrk · Nov 1, 2021 · db8505a · db8505a
1 parent 4528b34
commit db8505a
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Showing 9 changed files with 89 additions and 37 deletions.
diff --git a/scripts/openroad/or_cts.tcl b/scripts/openroad/or_cts.tcl
@@ -33,8 +33,8 @@ set max_slew [expr {$::env(SYNTH_MAX_TRAN) * 1e-9}]; # must convert to seconds
 set max_cap [expr {$::env(CTS_MAX_CAP) * 1e-12}]; # must convert to farad
 # set rc values
 source $::env(SCRIPTS_DIR)/openroad/or_set_rc.tcl 
-set_wire_rc -layer $::env(WIRE_RC_LAYER)
 estimate_parasitics -placement
+
 # Clone clock tree inverters next to register loads
 # so cts does not try to buffer the inverted clocks.
 repair_clock_inverters

diff --git a/scripts/openroad/or_groute.tcl b/scripts/openroad/or_groute.tcl
@@ -30,11 +30,25 @@ if { $::env(DIODE_INSERTION_STRATEGY) == 3 } {
  set_placement_padding -masters $::env(DIODE_CELL) -left $::env(DIODE_PADDING)
 }
 
-grt::check_routing_layer $::env(GLB_RT_MINLAYER)
-grt::set_min_layer $::env(GLB_RT_MINLAYER)
+set signal_min_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_MINLAYER)-1}]]
+set signal_max_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_MAXLAYER)-1}]]
 
-grt::check_routing_layer $::env(GLB_RT_MAXLAYER)
-grt::set_max_layer $::env(GLB_RT_MAXLAYER)
+if { ![info exists ::env(CLB_RT_CLOCK_MIN_LAYER)] } {
+ set clock_min_layer $signal_min_layer
+} else {
+ set clock_min_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_CLOCK_MINLAYER)-1}]]
+}
+
+if { ![info exists ::env(CLB_RT_CLOCK_MAX_LAYER)] } {
+ set clock_max_layer $signal_max_layer
+} else {
+ set clock_max_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_CLOCK_MAXLAYER)-1}]]
+}
+
+puts "\[INFO]: Setting singal min routig layer to: $signal_min_layer and clock min routing layer to $clock_min_layer. "
+puts "\[INFO]: Setting signal max routig layer to: $signal_max_layer and clock min routing layer to $clock_max_layer. "
+
+set_routing_layers -signal [subst $signal_min_layer]-[subst $signal_max_layer] -clock [subst $clock_min_layer]-[subst $clock_max_layer]
 
 grt::set_capacity_adjustment $::env(GLB_RT_ADJUSTMENT)
 
@@ -75,8 +89,8 @@ if {[info exists ::env(CLOCK_PORT)]} {
 
  # set rc values
  source $::env(SCRIPTS_DIR)/openroad/or_set_rc.tcl 
- set_wire_rc -layer $::env(WIRE_RC_LAYER)
  set_propagated_clock [all_clocks]
+ # estimate wire rc parasitics
  estimate_parasitics -global_routing
 
  set ::env(RUN_STANDALONE) 0

diff --git a/scripts/openroad/or_pdn.tcl b/scripts/openroad/or_pdn.tcl
@@ -42,9 +42,6 @@ if { $::env(FP_PDN_CHECK_NODES) } {
 if { $::env(FP_PDN_IRDROP) } {
  # set rc values
  source $::env(SCRIPTS_DIR)/openroad/or_set_rc.tcl 
- set_wire_rc -layer $::env(WIRE_RC_LAYER)
- set_wire_rc -signal -layer $::env(DATA_WIRE_RC_LAYER)
- set_wire_rc -clock -layer $::env(CLOCK_WIRE_RC_LAYER)
 
  analyze_power_grid -net $::env(VDD_NET) -outfile $::env(PGA_RPT_FILE)
 

diff --git a/scripts/openroad/or_rcx.tcl b/scripts/openroad/or_rcx.tcl
@@ -37,8 +37,6 @@ if { !$::env(RCX_MERGE_VIA_WIRE_RES) } {
 
 # set rc values
 source $::env(SCRIPTS_DIR)/openroad/or_set_rc.tcl 
-set_wire_rc -signal -layer $::env(DATA_WIRE_RC_LAYER)
-set_wire_rc -clock -layer $::env(CLOCK_WIRE_RC_LAYER)
 
 # RCX 
 define_process_corner -ext_model_index 0 X

diff --git a/scripts/openroad/or_replace.tcl b/scripts/openroad/or_replace.tcl
@@ -102,7 +102,6 @@ if {[info exists ::env(CLOCK_PORT)]} {
  read_sdc -echo $::env(CURRENT_SDC)
  # set rc values
  source $::env(SCRIPTS_DIR)/openroad/or_set_rc.tcl 
- set_wire_rc -layer $::env(WIRE_RC_LAYER)
  estimate_parasitics -placement
 
  set ::env(RUN_STANDALONE) 0

diff --git a/scripts/openroad/or_resizer.tcl b/scripts/openroad/or_resizer.tcl
@@ -28,12 +28,10 @@ if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
 
 read_sdc -echo $::env(CURRENT_SDC)
 
-# Resize
 # set rc values
 source $::env(SCRIPTS_DIR)/openroad/or_set_rc.tcl 
+
 # estimate wire rc parasitics
-set_wire_rc -signal -layer $::env(WIRE_RC_LAYER)
-set_wire_rc -clock -layer $::env(WIRE_RC_LAYER)
 estimate_parasitics -placement
 
 if { [info exists ::env(DONT_USE_CELLS)] } {
@@ -47,7 +45,7 @@ if { [info exists ::env(PL_RESIZER_BUFFER_INPUT_PORTS)] && $::env(PL_RESIZER_BUF
 if { [info exists ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS)] && $::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) } {
  buffer_ports -outputs
 }
-
+# Resize
 if { [info exists ::env(PL_RESIZER_MAX_WIRE_LENGTH)] && $::env(PL_RESIZER_MAX_WIRE_LENGTH) } {
  repair_design -max_wire_length $::env(PL_RESIZER_MAX_WIRE_LENGTH) \
  -slew_margin $::env(PL_RESIZER_MAX_SLEW_MARGIN) \
@@ -77,6 +75,7 @@ check_placement -verbose
 write_def $::env(SAVE_DEF)
 write_sdc $::env(SAVE_SDC)
 
-# Run STA
+# Run post design optimizations STA
+estimate_parasitics -placement
 set ::env(RUN_STANDALONE) 0
 source $::env(SCRIPTS_DIR)/openroad/or_sta.tcl 
diff --git a/scripts/openroad/or_resizer_routing_timing.tcl b/scripts/openroad/or_resizer_routing_timing.tcl
@@ -28,22 +28,64 @@ if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
 
 read_sdc -echo $::env(CURRENT_SDC)
 
-# Resize
-# estimate wire rc parasitics
-set_wire_rc -signal -layer $::env(WIRE_RC_LAYER)
-set_wire_rc -clock -layer $::env(WIRE_RC_LAYER)
-
 if { [info exists ::env(DONT_USE_CELLS)] } {
  set_dont_use $::env(DONT_USE_CELLS)
 }
 
-# CTS and detailed placement move instances, so update parasitic estimates.
-global_route
+set signal_min_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_MINLAYER)-1}]]
+set signal_max_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_MAXLAYER)-1}]]
+
+if { ![info exists ::env(CLB_RT_CLOCK_MIN_LAYER)] } {
+ set clock_min_layer $signal_min_layer
+} else {
+ set clock_min_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_CLOCK_MINLAYER)-1}]]
+}
+
+if { ![info exists ::env(CLB_RT_CLOCK_MAX_LAYER)] } {
+ set clock_max_layer $signal_max_layer
+} else {
+ set clock_max_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_CLOCK_MAXLAYER)-1}]]
+}
+
+puts "\[INFO]: Setting singal min routig layer to: $signal_min_layer and clock min routing layer to $clock_min_layer. "
+puts "\[INFO]: Setting signal max routig layer to: $signal_max_layer and clock min routing layer to $clock_max_layer. "
+
+set_routing_layers -signal [subst $signal_min_layer]-[subst $signal_max_layer] -clock [subst $clock_min_layer]-[subst $clock_max_layer]
+
+grt::set_capacity_adjustment $::env(GLB_RT_ADJUSTMENT)
+
+grt::add_layer_adjustment 1 $::env(GLB_RT_L1_ADJUSTMENT)
+grt::add_layer_adjustment 2 $::env(GLB_RT_L2_ADJUSTMENT)
+grt::add_layer_adjustment 3 $::env(GLB_RT_L3_ADJUSTMENT)
+if { $::env(GLB_RT_MAXLAYER) > 3 } {
+ grt::add_layer_adjustment 4 $::env(GLB_RT_L4_ADJUSTMENT)
+ if { $::env(GLB_RT_MAXLAYER) > 4 } {
+ grt::add_layer_adjustment 5 $::env(GLB_RT_L5_ADJUSTMENT)
+ if { $::env(GLB_RT_MAXLAYER) > 5 } {
+ grt::add_layer_adjustment 6 $::env(GLB_RT_L6_ADJUSTMENT)
+ }
+ }
+}
+
+if { $::env(GLB_RT_ALLOW_CONGESTION) == 1 } {
+ global_route -verbose 3\
+ -congestion_iterations $::env(GLB_RT_OVERFLOW_ITERS)\
+ -allow_congestion
+} else {
+ global_route -verbose 3 \
+ -congestion_iterations $::env(GLB_RT_OVERFLOW_ITERS)
+}
+
 # set rc values
 source $::env(SCRIPTS_DIR)/openroad/or_set_rc.tcl 
-estimate_parasitics -global_routing
+
 set_propagated_clock [all_clocks]
 
+# estimate wire rc parasitics
+estimate_parasitics -global_routing
+
+
+# Resize
 if { $::env(GLB_RESIZER_ALLOW_SETUP_VIOS) == 1} {
  if { [catch {repair_timing -hold -allow_setup_violations \
  -slack_margin $::env(GLB_RESIZER_HOLD_SLACK_MARGIN) \
@@ -81,6 +123,7 @@ check_placement -verbose
 write_def $::env(SAVE_DEF)
 write_sdc $::env(SAVE_SDC)
 
-# Run STA
+# Run post timing optimizations STA
+estimate_parasitics -global_routing
 set ::env(RUN_STANDALONE) 0
-source $::env(SCRIPTS_DIR)/openroad/or_sta.tcl 
+source $::env(SCRIPTS_DIR)/openroad/or_sta.tcl 
diff --git a/scripts/openroad/or_resizer_timing.tcl b/scripts/openroad/or_resizer_timing.tcl
@@ -28,22 +28,20 @@ if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
 
 read_sdc -echo $::env(CURRENT_SDC)
 
-# Resize
-# estimate wire rc parasitics
-set_wire_rc -signal -layer $::env(WIRE_RC_LAYER)
-set_wire_rc -clock -layer $::env(WIRE_RC_LAYER)
-
 if { [info exists ::env(DONT_USE_CELLS)] } {
  set_dont_use $::env(DONT_USE_CELLS)
 }
 
-# CTS and detailed placement move instances, so update parastic estimates.
 # set rc values
 source $::env(SCRIPTS_DIR)/openroad/or_set_rc.tcl 
-estimate_parasitics -placement
+
 set_propagated_clock [all_clocks]
 
+# CTS and detailed placement move instances, so update parastic estimates.
+# estimate wire rc parasitics
+estimate_parasitics -placement
 
+# Resize
 if { $::env(PL_RESIZER_ALLOW_SETUP_VIOS) == 1} {
  if { [catch {repair_timing -hold -allow_setup_violations \
  -slack_margin $::env(PL_RESIZER_HOLD_SLACK_MARGIN) \
@@ -68,18 +66,19 @@ if { [catch {repair_timing -setup \
 }
 
 set_placement_padding -global -right $::env(CELL_PAD)
-
 set_placement_padding -masters $::env(CELL_PAD_EXCLUDE) -right 0 -left 0
+
 detailed_placement
 if { [info exists ::env(PL_OPTIMIZE_MIRRORING)] && $::env(PL_OPTIMIZE_MIRRORING) } {
  optimize_mirroring
 }
+
 check_placement -verbose
 
 write_def $::env(SAVE_DEF)
 write_sdc $::env(SAVE_SDC)
 
-# Run STA
+# Run post timing optimizations STA
+estimate_parasitics -placement
 set ::env(RUN_STANDALONE) 0
-puts "Post-timing optimizations"
 source $::env(SCRIPTS_DIR)/openroad/or_sta.tcl 
diff --git a/scripts/openroad/or_set_rc.tcl b/scripts/openroad/or_set_rc.tcl
@@ -20,3 +20,6 @@ if { [info exist ::env(LAYERS_RC)] } {
  set_layer_rc -layer $layer_name -capacitance $capacitance -resistance $resistance
  }
 }
+
+set_wire_rc -signal -layer $::env(WIRE_RC_LAYER)
+set_wire_rc -clock -layer $::env(WIRE_RC_LAYER)