Skip to content
View wasinsangdam's full-sized avatar

Block or report wasinsangdam

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
wasinsangdam/README.md

Hi there 👋

Pinned Loading

  1. LeNet-5 LeNet-5 Public

    LeNet-5 on ZYBO Z7-10 FPGA

    C 4

  2. AMBA-AXI-Lite AMBA-AXI-Lite Public

    Implemented AXI-Lite interface slave and AXI-Lite interface BFM(Bus Functional Model) master.

    Verilog

  3. Systolic-Array Systolic-Array Public

    Implemented Systolic-Array that performs GEMM operation.

    Verilog 6

  4. riscv-emul riscv-emul Public

    RISC-V Emulator

    C++

  5. HDLBits HDLBits Public

    Verilog